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lucaj88
Visitor
Visitor
1,313 Views
Registered: ‎05-25-2019

Help with IP integrator Axi stream for Matrices Multiplication

Hello,

I want to test on a Pynq the matrix multiplication example provide in HLS.

I just made some changes, in particular I enable AXI interface for input and output and a pragma to pipeline functions and the testbench exit with no errors.

void matrix_multiply_top(const MATRIX_T A [A_ROWS][A_COLS],
                    const MATRIX_T B [B_ROWS][B_COLS],
                    MATRIX_T C[C_ROWS][C_COLS]){
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B
#pragma HLS INTERFACE axis port=C
#pragma HLS INTERFACE s_axilite port=return
#pragma HLS PIPELINE II=1
..
}

The block design is built according to the pdf attached.

The synthesis and the implementation ends without issues and let me to download the bitstream.

When I try to use it in pynq notebook, the DMA transfer seems in a deadlock state:

dma0 = overlay.axi_dma_0
dma1 = overlay.axi_dma_1

from pynq import Xlnk
import numpy as np

xlnk = Xlnk()
in_buffer0 = xlnk.cma_array(shape=(5,), dtype=np.uint32)
in_buffer1 = xlnk.cma_array(shape=(5,), dtype=np.uint32)
out_buffer = xlnk.cma_array(shape=(1,), dtype=np.uint32)

dma0.sendchannel.transfer(in_buffer0)
dma1.sendchannel.transfer(in_buffer1)
dma0.sendchannel.wait()
dma1.sendchannel.wait()

And the execution stucks here.

Can I assume that the HLS implementation of the is correct since testbench exit without error?

In this case the problem lays in the block design or in Pynq execution?

Can you suggest some reference for building accurate and efficient block design?

Thank you,

 

Luca

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demarco
Xilinx Employee
Xilinx Employee
1,274 Views
Registered: ‎10-04-2016

Hi @lucaj88 ,

I'm not a Phython expert, but don't you need to do something to set up the receive channel on dma0? I don't see out_buffer getting used anywhere in your code.

Regards,

Deanna

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lucaj88
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Registered: ‎05-25-2019

Yes, it should but anyway is stucked on sending stage.

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demarco
Xilinx Employee
Xilinx Employee
1,251 Views
Registered: ‎10-04-2016

Hi @lucaj88 ,

Depending on how your HLS IP works, you may not be able to receive data on the inbound path until your outbound path is primed to receive more data. The AXI DMA can store a few dwords of data on the S2MM path without configuration, but after that is will drop TREADY. This could potentially stall your system.

Besides, it's generally good coding practice to set up your receive path before enabling the transmit path.

Please add the necessary code to enable the DMA0 receive channel.

Regards,

Deanna

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