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kmshaw_saic
Observer
Observer
10,138 Views
Registered: ‎01-26-2011

How Do I Perform an AXI Burst in Software?

The AXI Reference Guide (UG761) states:

 

"AXI4 is for memory mapped interfaces and allows burst of up to 256 data transfer
cycles with just a single address phase."

 

My question is: How do I initiate a burst in software? Do I use memcpy() in C and a burst transfer is performed on the AXI bus? I've search online for an answer to this with no success.

 

Thanks,

 

Kevin

 

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7 Replies
muzaffer
Teacher
Teacher
10,126 Views
Registered: ‎03-31-2012

There is no mechanism which would cause a cpu to issue a burst. I am pretty sure even load/store multiple register instructions don't do it. The only option to initiate burst is to use some external hardware ie the dma controller on the arm processor (pl330) or an axi master built into the pl.
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dylan
Xilinx Employee
Xilinx Employee
10,122 Views
Registered: ‎07-30-2007

Bursts from a CPU are generally only issued by cache and related CPU hardware. So the short answer is to set the your MMU/translation table to be "normal" memory (versus peripheral or device memory), and then enable the cache. When the cache either fetches or evicts a cacheline, a burst will occur. Note that this also means that it is up to the CPU application to perform cache maintainance operations if the data must be moved out to the PL in a timely manner.

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chengtms
Observer
Observer
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Registered: ‎11-24-2012

I've tried doing that to an AXI peripheral in PL with the ldm and stm instrustions a while ago. I was able to generate burst read of 4 beats and burst write of 2 beats at most, even though I tried to read/write more registers. This was observed on hardware with Vivado logic analyzer. I was unable to generate longer burst to my AXI peripheral with software. Also, note that I was trying to burst to an AXI peripheral in PL, therefore I believe it doesn't involve any cache operation. Bursting to / from DRAM with software is another story, I don't think there is a way to force that.

 

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dylan
Xilinx Employee
Xilinx Employee
10,069 Views
Registered: ‎07-30-2007

The L2 cache controller has a 32-byte cache line. So the maximum you would usually expect to see at a 32-bit interface is a burst of 8 beats (there is a double cacheline mode for prefetching, but let's ignore that for now).

 

There is no difference from the CPU perspective of the PL and DRAM. It is all about how the MMU translation tables are configured.

 

See this Answer Record for how to mark the PL to be normal memory:

http://www.xilinx.com/support/answers/47406.html

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robertwilliam
Explorer
Explorer
4,878 Views
Registered: ‎09-28-2012

Hi,

 

I am new to 7 series. What is "pl" in the above posts?

 

 

Thanks,

 


"an axi master built into the pl."

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muzaffer
Teacher
Teacher
4,868 Views
Registered: ‎03-31-2012

It stands for Programmable Logic. In Zynq chips there is Processor Subsystem and PL.

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jeff_king
Explorer
Explorer
4,521 Views
Registered: ‎12-06-2013

@kmshaw_saic

 

memcpy() is the correct way to get the maximum burst rate from the the Zynq to the fabric using the AXI-GP bus. This question has come up in a lot of areas so maybe this will help others out. Here was my post from last year siting several other forms of the same question: HERE

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