06-18-2018 02:46 PM
I need implement an AXI4-lite master and some control logic to drive a AXI4-lite peripheral. I'm using xc7z020clg400-1 zynq FPGA, and using Vivado 2016.2. My AXI master must not be the embedded CPU in the FPGA chip.
I found Xilinx has a IP core of the AXI master which meets my requirement: LogiCORE IP AXI Master Lite v3.0 (PG161).
However in my Vivado GUI, under 'IP Catalog' I couldn't find this IP core. Can you please let me know how I can find it and integrate into my design?
06-18-2018 02:59 PM
You can reference the Vivado Design Suite Creating and Packaging Custom IP User Guide (UG1118; v2018.1) in Chapter 3: Using the Create and Package New IP Wizard.
From your Vivado IDE, you can select Tools --> Create and Package New IP... and follow the wizard instructions.
06-18-2018 04:24 PM
Thanks for your reply. I followed your steps and generated an AXI master.
However I didn't see an user guide generated. I'd like to know how to use this IP.
To be clear, I expect an user interface like the LogiCORE IP AXI Master Lite v3.0. That interface is very clear. I know how I put writing data on the bus along with valid signals and how to read data. I don't need drive AXI bus, the LogiCORE IP will connect its AXI master interface to my AXI slave peripheral.
But with the newly generated IP in Vivado, the user interface looks like an AXI interface, right? How do I drive this bus? Did I miss anything?