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Participant
Participant
481 Views
Registered: ‎01-21-2014

JTAG to AXI Master IP core maximum data transfer rate

Has anyone measured maximum data transfer rate of JTAG to AXI Master IP core (Tcl in Vivado) for given JTAG TCK and AXI ACLK?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @cioma,

The limiter will always be JTAG in this situation. The time to transfer the bits of the bulk transfer serially over JTAG would take much longer that the AXI clocks to perform the AXI transaction. 

Regards,

Deanna

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Participant
Participant
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Registered: ‎01-21-2014

Well, I'm particularly interested in the overhead that Vivado software and USB interface of the Xilinx Platform Cable add.

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