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Registered: ‎06-03-2019

Problem with the Simulation of the IP core AXI_AD7616, unable to write to the cmd or sdo fifo

Hi everyone! I would like to design in Vivado a custom AXI master to control the IP core "axi_ad7616" from ADI (https://wiki.analog.com/resources/fpga/docs/axi_ad7616). In the final project, I need to interface the ADC AD7616 with my Artix 7 FPGA using the SPI bus (serial mode). 

As a first step, I've decided to do a simulation just of the IP core to better understand its behaviour, therefore I have instantiated the component and prepared the attached testbench.vhd

In this simulation, my idea was to perform some register READ/WRITE operations in order to produce the desired output waveform from SDO. Unfortunately, as you can see from the waveforms below (and the attached files), I was not even able to write to the cmd_fifo or sdo_fifo. In the pictures, sdo_fifo_room and cmd_fifo_room are plotted and their values (representing the number of free entries in the FIFO) do not change after the WRITE operation. Instead, read/write operations to different registers (enable, reg_up_cntrl...) seem to be correctly performed.

Do you have any idea why is not working? An example of using this kind of ADI ip core or more documentation/link are also very appreciated.

The Register Maps I have used are reported here https://wiki.analog.com/resources/fpga/docs/axi_ad7616 and here https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi#register_map.

Thanks,

Andrea


axi.png wf1.pngwf2.png

wf1.png
wf2.png
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Registered: ‎05-21-2015

andrea.ragni@polimi.it,

Is there any way you can post your code?  It'd then be easier to figure out what's going on.

Dan

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Registered: ‎06-03-2019

I think to have finally solved the problem!

Thanks dgisselq for your interest, there should be already the VHDL file of the testbench in the first post. Let me know if you can not download it.

Regarding the solution:

In the wiki page of AXI SPI Engine (https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi) is stated that to enable the peripheral, the Enable Register (0x40) has to be set to 1.

I don't know if that is a mistake but I have found out that "up_sw_reset" become low (peripheral = enabled) when I load 0, and not 1, to the Enable register (address: 0x40) of AXI SPI engine.

You can see more details here: https://ez.analog.com/fpga/f/q-a/112898/problem-with-the-simulation-of-the-ip-core-axi_ad7616-unable-to-write-to-the-cmd-or-sdo-fifo.

I hope this can be useful if someone is working on the same IP core, please let me know if you also think there is an error in the documentation or it's just me misinterpreting something.

 

Andrea

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