02-04-2019 01:22 AM
I have an FPGA design controlled by a soft/hard CPU core (in Blockdesign) via AXI bus/interconnect. (Some uses Microblaze some uses ARM) I develop behavioral simulation the of the FPGAs.
How can I configure the FPGA block in simulator?
The first alternative seems the most elegant, so I go ahead planning this. How can I replace the MB with the VIP?
02-08-2019 07:03 AM - edited 02-08-2019 07:05 AM
That is one way to simulate a processor, by replacing the processor with the AXI VIP. To your option #2, I am not sure about loading SW into memory for the simulator as the HW hasn't been implemented at the point of simulation (or doesn't have to be) so I don't know how the simulator would handle adding SW into the system.
I don't think either of the ways you describe to replace MB with VIP are inheritly better or worst than you described, whether manually converting the block in the BD or using a TCL script. I don't know of any issues with using a TCL script in this way.
As an alternative to replacing MB with VIP, I do believe you could send certain data using the AXI VIP as Master to the (Slave) processor's (MB) registers which would configure the processor during simulation. I don't know how useful that is, but it would be one way to keep your processor in the system in your simulation design so you would only need to add/remove the VIP block while keeping the MB in the design at all times. You would still need to remove the VIP before implementation so I don't know if that would help more, depends on your use case.
If you haven't found it, the AXI VIP product guide is really helpful: https://www.xilinx.com/support/documentation/ip_documentation/axi_vip/v1_0/pg267-axi-vip.pdf
02-13-2019 06:39 AM
I have tried to run compiled SW using soft core CPU (however it was an openRisc not MicroBlaze, but it should work) I have wrore a script which converted the binary elf file into a memory initialization hex file.
I will write update of my experience.
02-13-2019 08:50 AM
Thanks for clarifying what you mean, and I understand what you are doing with SW (memory initialization wasn't what I was thinking at first).
When you do have an update I would be interested with what you find in terms of VIP setup.