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Visitor
Visitor
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Registered: ‎01-15-2019

XAxiDma_SimpleTransfer fail and AXI stream side band setting

Hi,

I'm trying to pass (9*1024*2+1)=18433  floating point data to my vivado hls generated ip and stream out only one float data to the dma and to the memory. I just followed the "xapp1170" example and set the axi stream interface with 

typedef ap_axiu<32,4,5,5> AXI_VAL

My problem is:

1. I know that it means User is 4 bits, Id is 5 bits and Dest is also 5 bits. But I don't know the meaning of user, id and dest and how should I set the width of them. 

2. My invoke of XAxiDma_SimpleTransfer failed in SDK but I don't know why. I just changed the stream length compared to xapp1170 and the input 2-d array is changed into 1-d array. I don't know whether it is because I wrongly set the width of user, id and dest. 

I will appreciate it very much if anyone can help me!

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @tomjames,

user, id and dest refer to signals that are part of the AXI Stream interface. If you don't know what they are for, odds are you can set them to zero and disable those signals. You can remove those signals and still have an AXI compliant interface.

For future reference:

tuser : this is for sideband information that is outside of the contents of tdata.

tid : usually this identifies which master the stream originated from

tdest : this is used to route the stream to the appropriate destination. If you had an 1 or more:N Stream Switch in your design, you would need to populate this signal so that the stream data goes to the correct slave.

The settings of these signals does not impact AXI DMA behavior. Can you query the AXI DMA status registers to see if it is throwing any errors? From your description, it is unclear whether the read (MM2S) or write (S2MM) path is failing. The registers to poke are at offsets 0x4 and 0x34 from the AXI DMA base address.

Regards,

Deanna

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