01-14-2016 06:07 PM
Recently, I am trying to learn the AXI Burst Mode or AXI Full Mode, which allows continuous data transaction between the PS and the PL on Zynq board. The general picture is as follows:
The objective is to move an array of data from the PS to the Slave IP through AXI bus in burst mode.
Although I alreadly know how to enable the AXI burst mode on the FPGA side (package my slave IP up with AXI Full/Burst interface verilog wrapper) through this video tutorial, I still get no idea about how to enable the AXI Full/Burst mode on the master side or the PS side. I really need to enable the AXI burst mode on the PS side, because somebody in this forum told me that the AXI burst transaction can be acheived only when both the PL and the PS have support for and enabled the AXI burst mode. Here is what he said:
" there is not much a peripheral/slave can do to have burst transactions generated onto it. After you code a slave which supports burst, you have to convince the master you are using to generate the burst transactions and DMA (in any disguise) is the only way to accomplish. I have seen indications that a memcpy can force the PS to generate it but I don't have any solid evidence for it. Another option is to try multi-register load/store operations in ARM."
So how to enable the AXI burst support in the PS/Master side so that I can have high-speed data transaction from the PS to the PL? Is there a detailed example or tutorial that I can follow?
01-24-2016 09:45 PM