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Visitor cpandya
Registered: ‎06-13-2018

AHB to AXI burst transfer doesn't work


I am working on small design. AHB2AXI_BARM shows overall block design of system. In this I am converting AHB signals into AXI and trying write and read to Block RAM.
I am trying to do burst write and read operation in Block Ram trough AXI interconnect. AHB2AXI data width is 64 bits and Master port of Interconnect is 512 bit wide data path.
When I am trying to write 8 burst (INCR8), I am missing last byte of data and second byte of data is being written twice.
Here I have attached three different timing simulation screen shots.
AHB2AXI_Slave_signals are slave input to AHB to AXI IP, AHB2AXI_Master_signals are Master output to AHB to AXI IP, BRAM_CTRL_Slave_signals is output slave signals of BRAM controller.
In BRAM_CTRL_Slave_signals image, 'hABCD_AAA6_BCBC_0002 data is begin written twice and 'hABCD_AAA6_BCBC_0007 is missing.

Can anybody help me with this?

Thanks in Advance!


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