11-01-2018 04:19 PM
My customer is running into an issue when simulating AXI VIP for Zynq 7000.
FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Time: 1094997500 ps Iteration: 8 Process: /axi_vip_pkg/axi_slv_wr_driver(C_AXI_PROTOCOL=1,C_AXI_WDATA_WIDTH=64,C_AXI_RDATA_WIDTH=64,C_AXI_WID_WIDTH=6,C_AXI_RID_WIDTH=6,C_AXI_HAS_REGION=0)::aw_channel/AW_CHANNEL
HDL Line: /wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv:3953
WARNING: [Simulator 45-29] Cannot open source file /wrk/2018.2/continuous/2018_06_14_2258646/packages/customer/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv: file does not exist.
run: Time (s): cpu = 00:02:13 ; elapsed = 00:14:15 . Memory (MB): peak = 2981.484 ; gain = 978.461
We found this AR for MPSoC:
AR# 71282: Fatal Error with MPSoC Verification IP (VIP) in 2018.2 Vivado Simulator on Windows
However, the workaround posted in the AR doesn't work. He was able to get past the issue by switching to Linux. But we'd like to know how to get around this error in Vivado on Windows. Has anyone else run into this?
11-13-2018 11:35 AM
If you are hitting the XSIM fatal error, it could be for any number of reasons not related to AR72182.
Please share this design if further debug is required.
11-28-2018 02:21 PM
Thanks for your response. I will work on getting the design files from my customer. Should I send them directly to you?