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Visitor jhbruhn
Registered: ‎06-01-2018

ARM to custom IP AXI Communication - no write transaction possible

Hello everyone,

I am currently working on the implementation of a Custom IP which is supposed to work with both MicroBlazes and the ARM Cores of a Zynq XC7Z020. The source code of said IP core can be seen here: https://gitlab.uni-oldenburg.de/zali1321/tt_fpga_arch_demo/blob/master/Implementation/ip_repo/sim/ni_fsm.vhd

Using the IP with MicroBlazes works flawlessly. Rerading from it from the ARM Core (connected to one of the GP ports) also functions correctly, but writing to it fails and leads to a data abort handler. I tried debugging the AXI Signal with a System ILA, but my results are very confusing: Read transaction can be seen as expected, but no Write Transactions, neither on the AW Signals or on the W Signals, are picked up by the ILA at all. I set a trigger to all signals so that my ILA would pick up every possible signal, but nothing happens. The ARM lands in the Data Abort Handler immediately. 

I also verified the adresses for correctness, they are indeed correct. Even Accessing the data region through a straight pointer, without utilization of the Xil_Out32 helpers does not yield any reaction in the ILA. The Driver code can be seen here: https://gitlab.uni-oldenburg.de/zali1321/tt_fpga_arch_demo/blob/master/Implementation/ip_repo/ni_drivers/drivers/network_interface_v1_00_a/src/network_interface.c#L25



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Scholar dgisselq
Registered: ‎05-21-2015

Re: ARM to custom IP AXI Communication - no write transaction possible


I think this screenshot shows a flaw in your design.


I could be wrong--I only spent about 20 minutes with SymbiYosys and this design, but I don't think the trace shown above was the intended functionaliity.

Within your design, I notice that several times you have items that depend upon *READY and *VALID and something else.  This is a bug.  Actions within AXI take place any time *READY and *VALID are true.  If your logic depends upon anything else, you will miss transactions as in your design above.

Your design also suffers from the read bug common to Xilinx's AXI-lite demonstration code.  You rewrote the write logic, so that's why you are have a different bug--otherwise Xilinx's AXI-lite demo code has a write bug in it as well

Check out this better demo of how to build an AXI-lite slave, together with the "proof" that it works.


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