08-12-2017 09:01 PM
I want to design a SG-DMA working in cyclic mode (moving data from device to memory in a continuous way). By now I have already designed a DMA system that works well in non cyclic mode. I have implemented the BD ring, and the last descriptor points to the first one. I have included XAxiDMA_SelectCyclicMode instruction to get the DMA run again over the BD ring if it continue receiving packages from the device. However, when I execute the code the system only progresses until all BD have been processed one time, and then stops. I assume that a fast way to solve this would be submitting BDs to the hardware again using XAxiDMA_BdRingToHw, but definitely it doesn’t seem the most elegant way to get cyclic operation. I work with a ZC702 demoboard and VIVADO 2016.3
08-13-2017 12:57 AM
@cjmartin All the searches I did result in Linux patches that handle the restart in software.
Check out "known issues" on the axi dma wiki:
08-13-2017 05:51 PM
You could possibly write some HLS code to stream continuously to memory. It would not be so hard and would be autonomous.
09-02-2017 06:08 PM
There would be some significant difference between programming the DMA SG directly writing on the core registers rather than using the API provided with the BSP? According to some tutorials I have found on internet, it seems that cyclic mode works well if DMA is configured directly, bypassing the API functions, but I am not sure if API performs some additional task that should be taken into account to make DMA works properly (particularly those related with cache managing).
Thanks a lot.
09-02-2017 09:33 PM
@cjmartin I have not had the need to do it in this particular case but I am sure it would work as well with a custom master.
In the end it is all AXI commands over the wire.
04-16-2018 01:17 AM
Before call the function XAxiDMA_SelectCyclicMode, did you call XAxiDma_BdRingEnableCyclicDMA? It is enable Cyclic DMA Mode, enable the RingPtr-->Cyclic=1.
I also have a question, in the Cyclic Mode ,PS sends the buffer's datas continously from the first BD to the last BD, then the buffer's datas refeshed or not for the second sending?