AXI DMA simulation (ZYNQ UltraScale+ MPSoC)

[patopat]

Hi,

My design is quiet simple:

The Xilinx IP I2S receiver (with internal fifo) is connected to an AXI_DMA in order to transfer the Data stream in DDR.

I known there is the scatter/Gather DMA mode to offload the PS but there are buffers descriptor in memory still need to be programmed by the PS.

Could you tell me the way to simulate in behavioral mode, a design containing an AXI DMA IP without PS intervention ? 

Pat

[demarco · Accepted solution]

Hi @patopat,

The easiest way I can think of to do this is to use the MPSoC US+ Verification IP to perform the register reads/writes to configure the AXI DMA.  

https://www.xilinx.com/support/documentation/ip_documentation/zynq_ultra_ps_e_vip/v1_0/ds941-zynq-ultra-ps-e-vip.pdf

The write_data function will send AXI writes out the PS-PL master port to the AXI DMA.

You would also use the MPSoC VIP to configure memory with buffer descriptors if you want to simulate the AXI DMA in Scatter Gather mode. The MPSoC VIP has backdoor memory write from file functions to program the DRAM memory model. You could create a text file with the buffer descriptors and use the pre_load_mem_from_file function to load it into PS DDR.

Regards,

Deanna

[patopat]

Hi @demarco,

What is the easiest way to generate buffer descriptor memory contents ?

I was wondering if a "user-friendly generator" tool exists ? Something similar to the xaxidma API from SDK but generate a text file directly which can be loaded in the memory.

Best regards,

Pat

[demarco]

Hi Pat,

Xilinx doesn't have a widget to do this for you. It's all manual.

Regards,

Deanna