AXI Master to Multiple Slaves with Same Address?

[bfung]

Wondering if this is possible: multiple AXI slave devices (with all the same addresses) connected to an interconnect with one master device. This is such to allow the master to issue one command and have all the slave devices respond in (almost) parallel. In other words, to allow the master to write the same data simultaneously to all slave devices. The master sits on one-board and the slaves are distributed on multiple boards which are connected to the master using Aurora 64/66B and Chip2Chip. 

If it isn't possible to achieve this with the Xilinx AXI IPs, how does one create an architecture to allow this?

Thanks. 

[dgisselq]

@bfung,

I suppose it's possible--but only from the standpoint that anything is possible.  I think, however, that the meaning of what it does would need to be very application dependent.  Some questions that would need to be addressed include:

• When you read from this multiperipheral address, what value gets returned?
• Will all of the slaves respond in the exact same amount of time, with the exact same number of stalls, or will the multiperipheral need logic to force the bus to wait for the slowest device to respond before moving forward with the bus protocol?

Dan

[bfung]

These slave peripherals are all identical and just perform work, they don't return any values. 

I am looking to send control signals to all of these peripherals at once, such that there is some sort of parallelism between them all. I can account for differences in timing between peripherals if necessary and if they're repeatable. Once all peripherals are finished running, the data they wrote to RAM is read. 

I'm stuck with an AXI interface using Aurora & chip2chip from the master to each slave device, so I'm thinking there's no easy way around it than to send these signals over AXI?

Any suggestions are welcomed!

[dgisselq]

If your slave(s) will never stall, why not use a simpler interface?

Here's an AXI bridge to a simpler interface:

• Any time o_we is true, a write is requested of the external peripheral(s).  The write is assumed to take one clock, and not allowed to stall.  The address is given by o_waddr, data by o_wdata, and bit selects by o_wstrb
• Same thing for o_rd.  Anytime o_rd is true, the core wishes to read from your peripheral.  o_raddr will be set to the address you wish to read from.  The value needs to be returned in one clock, and only ever changed if o_rd was true.

Sounds like you could easily wire something like this up to all of your peripherals, and then skip the AXI protocol to all but the bus bridge.

Dan

[vanmierlo]

A standard AXI interconnect will not support this since it routes based on address ranges. But if you're willing to create one yourself you could concoct this. You will have to wait for the slowest device before you acknowledge back to your master. If they are all equally fast that should not matter.

[bfung]

Great. With some slight creativity, I created my own by simply duplicating the axi_w, axi_aw, and axi_b lines for strictly writing to multiple devices.