03-20-2018 02:32 PM
I am using Vivado 2017.3 and Riviera-PRO version 2017.10.67.6735 built for Linux64
I am running into an issue when ARESETN is disabled on AXI Smartconnect v1.0 (i.e. HAS_ARESETN=0). The issue is as follows:
1) Assert WVALID and AWVALID at the Slave side of the Smartconnect; WREADY and AWREADY are asserted as well.
2) A number of clock cycles later, WVALID and AWVALID are asserted on the Master side; WREADY and AWREADY are asserted as well.
3) After WVALID and AWVALID fall, BVALID is asserted on the Master side of the smartconnect.
However, BVALID is never asserted on the Slave side.
If the ARESETN port is enabled and connected, I do not run into this issue.
With ARESETN enabled and connected...
With ARESETN disabled...
03-27-2018 04:20 PM
I tried running a simple simulation with SmartConnect configured with HAS_RESETN=0. I could not reproduce this problem with Vivado Simulator or Questa. The SmartConnect in my simulation had one slave interface and one master interface.
Are you able to run this test bench in Vivado Simulator? Do you see the same results?
03-28-2018 11:53 AM
Thanks for looking into this, Deanna.
I tried the setup you suggested and found the same results as you; the BVALID signal was received on the slave side of the smartconnect. At this point I'm still simulating with Riviera.
I was able to recreate the issue using 1-Slave:2-Masters. In this setup, I have 3 clocks, such that each interface receives its own clock, each operating at a different frequency...
Can you verify that you get the same results under this setup?