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270 Views
Registered: ‎12-14-2018

AXI-Stream data FIFO behavior

There is a data producer that always produce a data and a data cunsumer that always consume the data and an axis data fifo between them. I expect that there will not be any delays between the entering the data into fifo and leaving it. But actually it is. But why?

There is the simulation of the above:

screenshot_3.png

1. Why there is gaps between data consuming by axis data fifo. Experimentally I found out that the width of consuming window is equal to width of initial reset. (But why?) And due to the axis data fifo has a period of data consuming equal to 51 cycles and doesn't depend on fifo depth it is sufficient to make 51 cycles of reset to make the fifo work without a breach of continuity. But why there is exactly 51 cycles and how it depends on the parameter of axis data fifo?
2. Why there is gaps between data consuming and data producing by axis data fifo? There is exactly 153 cycles (3*51) and doesn't depend on fifo depth (But in packet mod it requires 204 cycles and sometimes works incorrect). But why there is any? According to pg085 "The FIFO when configured in normal mode outputs data as soon as it is possible."

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2 Replies
Voyager
Voyager
234 Views
Registered: ‎02-01-2013

Re: AXI-Stream data FIFO behavior

 

What are your M_AXI and S_AXI clock speeds?

Does the problem still occur if you clock it slower than 1,000,000,000,000 Hz--which is what you appear to be doing in the sim?

-Joe G.

 

219 Views
Registered: ‎12-14-2018

Re: AXI-Stream data FIFO behavior

The problem seems to be solved with lower frequences. I didn't know it make sence to simulation and still don't understand why.

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