We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor jeeva91
Registered: ‎02-12-2019

AXI Stream post synthesis simulation fail (Tlast isssue)

I am trying to generate an AXI Stream Master to be fed to the AXI-DMA module. Here are my inputs, output and the logic
1. Single pulse (TdcRegReadySend) whenever there is new data to be sent to the DMA
2. Datain (32 bit) data to be sent
3. Tready from the Axi-Stream
Axi Stream with
1. Tvalid whenever there is single pulse (TdcRegReadySend)
2. Tlast after 4 transfers
3. Tdata copy of the Datain
I have attached my project and also the FSM and behavioral and post synthesis simulation image. 

The behavioral simulation works as expected but the systhesis simulation failed as it does not see TLast.  My guess is on the timing constraint as we do not have any timing specification now. My second guess is on the way we have the counter for packet size inside the SendStreamData state. 

Please suggest us some ways to debug this problem. Thank you. 

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: AXI Stream post synthesis simulation fail (Tlast isssue)

Hi @jeeva91 ,

I took a look at the waveforms in your design and it looks like the TKEEP field is missing bits. There should be one TKEEP bit for every data byte. It looks like you data bus is 32-bits, so I would expect 4 TKEEP bits. I'm not sure what the tools might optimize away if this field is not the correct size.

Another thing you can do is add a Protocol Checker IP to your design. If there is some else that isn't logically correct in your IP, it can help narrow down the issue quickly.




Don’t forget to reply, kudo, and accept as solution.
0 Kudos