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Visitor andrea96b
Visitor
282 Views
Registered: ‎03-25-2019

AXI custom IP with interrupt support

Hi, I have a problem understanding how the axi interrupt support work.

I have a uart like IP that generate 2 interrupt, one when a signal named RDA is high, and one when a signal named TBE has a rising edge.

I have modified the generated interrupt support file like this.


Section where I've added the logic of interrupt generation.

	process( S_AXI_ACLK ) is                                                           
	  begin                                                                            
	    if (rising_edge (S_AXI_ACLK)) then                                             
	      if ( S_AXI_ARESETN = '0') then                                               
	        intr <= (others => '0');                                                   
	      else 
	                                                                              
	          intr <= RDA & TBE;                                                                                               
	      end if;                                                                      
	    end if;                                                                        
	end process;     

Configuration parameters

		-- Width of S_AXI data bus
		C_S_AXI_DATA_WIDTH	: integer	:= 32;
		-- Width of S_AXI address bus
		C_S_AXI_ADDR_WIDTH	: integer	:= 5;
		-- Number of Interrupts
		C_NUM_OF_INTR	: integer	:= 2;
		-- Each bit corresponds to Sensitivity of interrupt :  0 - EDGE, 1 - LEVEL
		C_INTR_SENSITIVITY	: std_logic_vector	:= x"FFFFFFFE";
		-- Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]
		C_INTR_ACTIVE_STATE	: std_logic_vector	:= x"FFFFFFFF";
		-- Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL
		C_IRQ_SENSITIVITY	: integer	:= 1;
		-- Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]
		C_IRQ_ACTIVE_STATE	: integer	:= 1

The problem is that the interrupt for the signal TBE seems to be generated as it were level interrupt instead of edge triggered. I've also created a testbench where to be sure I've setted all the interrupt to edge triggered.

The irq signal rise up immediately when I enable the interrupt without any rising edge.

2019-06-02_18-07.png

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1 Reply
Scholar dgisselq
Scholar
212 Views
Registered: ‎05-21-2015

Re: AXI custom IP with interrupt support

I must be missing something.  I tried to recreate your results, and just got errors about how the `s_irq` net is being driven by constants from multiple places.

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