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AXI stream clock converter tlast issue

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Visitor
Posts: 7
Registered: ‎10-25-2017
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AXI stream clock converter tlast issue

Hi all,

I'm using a AXI4-Stream Clock converter in my design. VIvado is 2017.2.

The IP is customized in this way:

 

img_1.jpg

 

The simulation result is in following image:

 

 

img_2.jpg

 

It seems that "m_axis_tlast" remain stucked to high while "s_axis_tlast" go low after one "s_axis_aclk" clock cycle.

Clock frequencies are: s_axis_aclk = 100MHz,    m_axis_aclk = 125MHz.

 

Can someone help me in this issue?

Thanks

 


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Voyager
Posts: 324
Registered: ‎04-21-2014

Re: AXI stream clock converter tlast issue

tlast and tdata is also held.

 

My working understanding is that TLAST and TDATA are only significant when TVALID and TREADY are sampled high.  Does it go low the next time TVALID and TREADY are high?

 

Does the design otherwise work, and this is just an observation of an unanticipated behavior?

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***

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Voyager
Posts: 324
Registered: ‎04-21-2014

Re: AXI stream clock converter tlast issue

tlast and tdata is also held.

 

My working understanding is that TLAST and TDATA are only significant when TVALID and TREADY are sampled high.  Does it go low the next time TVALID and TREADY are high?

 

Does the design otherwise work, and this is just an observation of an unanticipated behavior?

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
Visitor
Posts: 7
Registered: ‎10-25-2017

Re: AXI stream clock converter tlast issue

Hi Morgan,

 

you are right and your understanding it's also mine, but TLAST remain high also next time TVALID and TREADY are HIGH after to have been LOW.

At the moment the design is only simulated and it has not  yet tried in hardware.

Visitor
Posts: 7
Registered: ‎10-25-2017

Re: AXI stream clock converter tlast issue

Hi Morgan, you was right, it was a mistake in my testbench.

Next time TVALID and TREADY has sampled HIGH, TLAST and TDATA are updated.

Thanks