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Visitor jawkover
Visitor
144 Views
Registered: ‎12-10-2018

AXI4 Peripheral Lite slave Selftest error

Dear,

 

We are trying to create a connection between the MicroBlaze CPU and our VHDL code and found the AXI4 peripheral creator. We created an AXI4 Lite slave ip core and modified some values to make it so that the registers that are changed by the MB CPU, are directly connected to our VHDL outputs/inputs.

 

Our test AXI4 peripheral had 3 registers (32 bit) and worked flawlessly. We then created a larger peripheral with 8 registers (32 bit) based on the exact same structure, just with more slv_regs but it doesn't work. The selftest reports "Error reading register value at address BASE_ADDRESS_LOW". Meaning that slv_reg0 fails.

Vivado did mentioned this which got me worried:

WARNING: [Synth 8-6014] Unused sequential element slv_reg0_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:227]
WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:228]
WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:229]
WARNING: [Synth 8-6014] Unused sequential element slv_reg3_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:230]
WARNING: [Synth 8-6014] Unused sequential element loc_addr_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:236]

 

Is the method that I am using to get a bridge between the MB and VHDL code valid? Or is there a more proper method? I couldn't find an official method within the AXI4 library.

I have included the IP core as a zip.

 

Thanks!

Kind regards,

 

Jonathan

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6 Replies
Explorer
Explorer
121 Views
Registered: ‎05-21-2015

Re: AXI4 Peripheral Lite slave Selftest error

@jawkover,

I took the time this morning to apply a formal evaluation of your code.  I found only two basic issues, both associated with the code the peripheral creator generates, and neither likely to be your issue today.

I did notice that the slv_reg0-slv_reg3 registers within your core are set, but never read.  Instead, your code reads values output_1-output_4 from these addresses.  This could easily be the reason a self-test of register 0 would fail.

Dan

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Visitor jawkover
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Registered: ‎12-10-2018

Re: AXI4 Peripheral Lite slave Selftest error

 

@dgisselq 

Thanks for your reply!

That is indeed true. I require full duplex communication between MB and VHDL. Is this a proper method or should I use a signal to load the slv_regx into the output_x and then output_x into the reg_data_out? This would give meaning to slv_reg0-3 again.

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Explorer
Explorer
112 Views
Registered: ‎05-21-2015

Re: AXI4 Peripheral Lite slave Selftest error

@jawkover,

I don't see a problem with it myself.  AXI requires that all outputs be need registered, and your core is doing that.  See S_AXI_RDATA signal for example.  I might clean the core up a touch and get rid of the slv_regs you aren't using, perhaps even adjust the self-test so that it passes, but other than that it looks fine to me.

Dan

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Visitor jawkover
Visitor
109 Views
Registered: ‎12-10-2018

Re: AXI4 Peripheral Lite slave Selftest error

@dgisselq 

True, but the problem is that the selftest writes to all the registers and then reads from them. If the written and read values are the same, then the AXI4 peripheral is working correctly. With the selftest failing and my program not working properly, I fear that something went wrong with the AXI4 periph.

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Visitor jawkover
Visitor
60 Views
Registered: ‎12-10-2018

Re: AXI4 Peripheral Lite slave Selftest error

Furthermore, I find this warning a bit worrysome:

WARNING: [Synth 8-6014] Unused sequential element loc_addr_reg was removed. [c:/PROJECT_RETRIM/Retrim_R03/Retrim_R03.srcs/sources_1/bd/Retrim_R03/ipshared/c1cd/hdl/MB_Interconnect_v1_0_MB_INTERC_R01.vhd:236]

loc_addr is the key for the switch case:

	process (output_1, output_2, output_3, output_4, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
	variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
	begin
	    -- Address decoding for reading registers
	    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
	    case loc_addr is
	      when b"000" =>
	        reg_data_out <= output_1;
	      when b"001" =>
	        reg_data_out <= output_2;
	      when b"010" =>
	        reg_data_out <= output_3;
	      when b"011" =>
	        reg_data_out <= output_4;
	      when b"100" =>
	        reg_data_out <= slv_reg4;
	      when b"101" =>
	        reg_data_out <= slv_reg5;
	      when b"110" =>
	        reg_data_out <= slv_reg6;
	      when b"111" =>
	        reg_data_out <= slv_reg7;
	      when others =>
	        reg_data_out  <= (others => '0');
	    end case;
	end process; 

If it indeed means that the register of the key to that switch case is removed then it could explain why the registers aren't accessible anymore. If I read that write, that is.

 

Jonathan

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Explorer
Explorer
25 Views
Registered: ‎05-21-2015

Re: AXI4 Peripheral Lite slave Selftest error

Yeah, that looks ominous.  I'm guessing that the warning is a nothingburger, just there to let you know that loc_addr is used internally within that process and never elsewhere, so it can be successfully optimized away (once your logic is implemented).

Dan

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