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Visitor panikplauze
Visitor
353 Views
Registered: ‎12-05-2018

AXI4 Read/Write Ordering of Multiple Masters

Hi!

After reading through the chapters 5 and 6 of the AMBA AXI spec I would like to to ask you if I understand the AXI correctly. My system has a AXI4 master which writes to a memory. A second AXI4 master reads that data from the same memory address asynchronously. Data transfer size is 512 bytes (64 bit bus) for both directions. The both masters and the slave memory are connected via an AXI Interconnect with clock rate conversion.

My basic question is: Is there a guarantee that any transfer of the writing master is completed before the reading master can read? Or: Can a 512 byte write/read transfer be interrupted?

A5.3 "Transactions from different masters have no ordering restrictions. They can complete in any order."

A5.3.4: "AXI has no ordering restrictions between read and write transactions. They can complete in any order, even if the ARID value of a read transaction is the same as the AWID value of a write transaction."

The ordering isn't critical in my case. Does "can complete in any order" that a 512 byte transfer is guaranteed to be completed?

A6.1: "In an AXI system with multiple masters, the AXI IDs used for the ordering model include the infrastructure IDs, that identify each master uniquely. This means the ordering model applies independently to each master in the system."

So if the 512 byte write transfer would be transfered in smaller portions the order is guaranteed. But I assume that the reading master can interfere here? If so, is it possible to optimize the access by giving the writing master a higher priority?

Capter 7 confuses me completely...

Can anyone please help?

Best Regards

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4 Replies
Visitor panikplauze
Visitor
315 Views
Registered: ‎12-05-2018

Re: AXI4 Read/Write Ordering of Multiple Masters

Is the question too trivial? I would be glad if someone could give me a literature hint.

Best Regards

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Explorer
Explorer
285 Views
Registered: ‎03-31-2016

Re: AXI4 Read/Write Ordering of Multiple Masters

For AXI, reads and writes are treated as completely independent.  Therefor we cannot answer your question with the information provided.

The ordering to the memory would depend on the implementation details of the memory controller and potentially the interconnect, depending on configuration.

For the Interconnect's impact you should look at the details of the Xilinx AXI Interconnect IP documentation.  There are too many options to list out in a forum post but basically a high performance configuration would allow the reads and writes at the same time but an low performance/low resource option would have some arbitration.

But that is just want the interconnect can do,  it is up to the memory controller to support that.

 

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Visitor panikplauze
Visitor
266 Views
Registered: ‎12-05-2018

Re: AXI4 Read/Write Ordering of Multiple Masters

@necare81

Thanks for your reply. You're right, the answer depends on many factors of the design.

After debugging I can answer the basic question myself. 

My basic question is: Is there a guarantee that any transfer of the writing master is completed before the reading master can read? Or: Can a 512 byte write/read transfer be interrupted?

No, since AXI4 there is no guarantee because "locked access" was removed from AXI4 spec and "exclusive access" isn't implemented in Xilinx IP's. 512 byte transfers are subdivided in bursts. Any burst is completed without interruption. But between bursts another transfer can take place. This can be manually optimized by setting prioritization in the AXI Interconnect IP, e.g. writing masters have higher prio, but in this case only uninterrupted writing is guaranteed - read accesses might be interrupted due to lower priority.

So unforunatly I have to implement double buffering in order to guarantee data integrity. But currently I'm struggeling how to pass the information of the current page to read between the asynchronous processes...?

Any other ideas?

Best Regards

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Voyager
Voyager
211 Views
Registered: ‎02-01-2013

Re: AXI4 Read/Write Ordering of Multiple Masters

Guaranteeing order, is what FIFOs do best.

If you're talking about only 512-byte chunks of data, why not just use a FIFO to pass data between the write process and the read process?

That aside, check the Memory Type (AWCACHE) attribute driven by the write process. If you're initiating a 512-byte transfer with the memory type set to "Device Non-bufferable" [0000], you won't get a response from the AXI Interconnect until the (whole) write completes at the destination. You could use that certainty to send an indication from the write process (through a FIFO) to the read process to let it know the data can be read.

-Joe G.