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Visitor tomjames
Visitor
253 Views
Registered: ‎01-15-2019

Axi Master IP accessing PS Memory on ZedBoard

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Hi,

I'm new to Vivado hls and Zynq. I want to create a convolution accelerator using Vivado hls and apply it to ZedBoard(ZC702). The Vivado hls top level function is:

void hls_conv(
		float *InImg,
		float *InWeight,
		float *InBias,
		int Stride,
		int InWidth,
		int WeightSize,
		int WeightNum,
		int InDepth,
		float *OutImg);

What I want to do is to let the PS pass the first address of the arrays and the integer values to the hls IP and then the hls IP acquire the control of the PS memory and output the result into the array called "OutImg". The process of the function contains random array access which is not sequencial. I added the following directives to the ports:

#pragma HLS INTERFACE s_axilite port=OutImg
#pragma HLS INTERFACE s_axilite port=InBias
#pragma HLS INTERFACE s_axilite port=InWeight
#pragma HLS INTERFACE s_axilite port=InImg

#pragma HLS INTERFACE s_axilite port=InDepth bundle=control
#pragma HLS INTERFACE s_axilite port=WeightNum bundle=control
#pragma HLS INTERFACE s_axilite port=WeightSize bundle=control
#pragma HLS INTERFACE s_axilite port=InWidth bundle=control
#pragma HLS INTERFACE s_axilite port=Stride bundle=control
#pragma HLS INTERFACE s_axilite port=return bundle=control

#pragma HLS INTERFACE m_axi depth=3211264 port=OutImg offset=slave bundle=gmem
#pragma HLS INTERFACE m_axi depth=1024 port=InBias offset=slave bundle=gmem
#pragma HLS INTERFACE m_axi depth=4718592 port=InWeight offset=slave bundle=gmem
#pragma HLS INTERFACE m_axi depth=3211264 port=InImg offset=slave bundle=gmem

The CoSimulation runs well and I got the desired result. Then I exported it into an IP for use of the IP integrator. The following picture shows my block design:

Screenshot from 2019-03-15 21-16-24.png

I enabled the HP slave AXI Interface of S AXI HP0 with 32-bit width for use of the m_axi_gmem port of my IP and fabricated the PL-PS IRQ_F2P interrupt. After synthesis and Implementation. I exported the hardware and lunched SDK. I used "XHls_conv_set...()" function to pass the value of the integers and the first address of the arrays to the IP and run "Hls_conv_Start()" to start it and use the following loop to wait for interrupt:

do {
         ;
      }while(!XHls_conv_InterruptGetStatus(&HlsConv));

However, it seems that the program never got out of the loop and stuck there. I tried another way to determine whether the job is done using:

do {
          ;
      } while (!XHls_conv_IsReady(&HlsConv));

The program got out of the loop very quickly and the OutImg array seems to be unchanged. 

I set the clock period of the hls IP to 10 ns. The CPU clock is 666MHz and the DDR clock is 533MHz. I created PL Fabric Clock to 100MHz. I didn't know where I went wrong. Can anyone help me with this problem? I will appreciate it very much if you can help me!

The attached is my vivado hls design file, tb file and my sdk software file.

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Xilinx Employee
Xilinx Employee
151 Views
Registered: ‎10-04-2016

Re: Axi Master IP accessing PS Memory on ZedBoard

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Hi @tomjames,

One way to start debugging this is to see what the AXI interfaces on your HLS IP are doing and seeing if those transactions make sense.

The place to start is by inserting System ILAs on the s_axi_control and m_axi_gmem interfaces of hls_conv. I'd also add one on the M00_AXI interface of the axi_smc (the SmartConnect).

Chapter 6 of UG994 walks through the insertion of System ILAs:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug994-vivado-ip-subsystems.pdf#page=125

Lab 5 of UG936 shows how to use the Vivado Logic Analyzer to take traces. Please write back if you need help configuring a trigger.

https://www.xilinx.com/member/forms/download/design-license.html?cid=3c4709de-dedb-479d-a089-ebbd6133dac1&filename=ug936-vivado-tutorial-programming-debugging.pdf#page=49

Regards,

Deanna

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2 Replies
Xilinx Employee
Xilinx Employee
152 Views
Registered: ‎10-04-2016

Re: Axi Master IP accessing PS Memory on ZedBoard

Jump to solution

Hi @tomjames,

One way to start debugging this is to see what the AXI interfaces on your HLS IP are doing and seeing if those transactions make sense.

The place to start is by inserting System ILAs on the s_axi_control and m_axi_gmem interfaces of hls_conv. I'd also add one on the M00_AXI interface of the axi_smc (the SmartConnect).

Chapter 6 of UG994 walks through the insertion of System ILAs:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug994-vivado-ip-subsystems.pdf#page=125

Lab 5 of UG936 shows how to use the Vivado Logic Analyzer to take traces. Please write back if you need help configuring a trigger.

https://www.xilinx.com/member/forms/download/design-license.html?cid=3c4709de-dedb-479d-a089-ebbd6133dac1&filename=ug936-vivado-tutorial-programming-debugging.pdf#page=49

Regards,

Deanna

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Visitor tomjames
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131 Views
Registered: ‎01-15-2019

Re: Axi Master IP accessing PS Memory on ZedBoard

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Thank you very much for the debugging method. I changed my mind to use the axi stream as my module interface. I will try to get my axi master module work if I get time.

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