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Contributor
Contributor
486 Views
Registered: ‎07-04-2017

Axi Write transaction error

Hello everyone,

 

I have created a custom ip with a master and a slave interfaces. I just add the following codes to master and change START_DATA_VALUE and Target Slave Base Addr to 0x0000_0000 

 

reg state; // It isn't used night now
initial begin
state <= 1'b1;
start_single_write <= 1'b1;
end
  //Write Addresses
	  always @(posedge M_AXI_ACLK)
	      begin
	        if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)
	          begin
	            axi_awaddr <= 0;
	          end
	          // Signals a new write address/ write data is
	          // available by user logic
	        else if (M_AXI_AWREADY && axi_awvalid)
	          begin
	            //axi_awaddr <= axi_awaddr + 32'h00000004;
	             axi_awaddr <= 32'h00AA_BABA;
	          end
	      end

	  // Write data generation
	  always @(posedge M_AXI_ACLK)
	      begin
	        if (M_AXI_ARESETN == 0 || init_txn_pulse == 1'b1 )
	          begin
	            axi_wdata <= C_M_START_DATA_VALUE;
	          end
	        // Signals a new write address/ write data is
	        // available by user logic
	        else if (M_AXI_WREADY && axi_wvalid)
	          begin
	           // axi_wdata <= C_M_START_DATA_VALUE + write_index;
	           axi_wdata <= 32'hBABABABA;
	          end
	        end

	  //Read Addresses
	  always @(posedge M_AXI_ACLK)
	      begin
	        if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)
	          begin
	            axi_araddr <= 0;
	          end
	          // Signals a new write address/ write data is
	          // available by user logic
	        else if (M_AXI_ARREADY && axi_arvalid)
	          begin
	            //axi_araddr <= axi_araddr + 32'h00000004;
							axi_araddr <= 32'h00AA_BABA;


	          end
	      end



	  always @(posedge M_AXI_ACLK)
	      begin
	        if (M_AXI_ARESETN == 0  || init_txn_pulse == 1'b1)
	          begin
	            expected_rdata <= C_M_START_DATA_VALUE;
	          end
	          // Signals a new write address/ write data is
	          // available by user logic
	        else if (M_AXI_RVALID && axi_rready)
	          begin
	            expected_rdata <= 32'hBABABABA;
	          end
	      end

 

I ran simulation and this is the result:

vivado_sim.png

 

Device: Zybo

OS: Xubuntu 16.04

 

Thank you

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2 Replies
Explorer
Explorer
478 Views
Registered: ‎09-07-2011

Re: Axi Write transaction error

Double check your handshakes.   For example, the master should assert M_AXI_AWADDR  along with M_AXI_AWVALID.    It does this until the slave asserts  M_AXI_AWREADY.   

 

The "ready"  is really an "acknowledge" to finish the current handshake.  The fact it's called 'ready' is a little misleading I find.   Maybe it should be called "already"... "I got your data already"....    

 

 

 

 

 

 

 

Contributor
Contributor
469 Views
Registered: ‎07-04-2017

Re: Axi Write transaction error

@geoffbarnes Thank you for your reply. The problem is that M_AXI_WREADY is not asserted. I tried to change it in the code but it gave error. Also my design is in the attachment if it's help.

 

design.png

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