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Axidma IOC interrupt is not asserted in SG mode

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Visitor
Posts: 3
Registered: ‎05-15-2018
Accepted Solution

Axidma IOC interrupt is not asserted in SG mode

Hi,

 

I am experimenting with an Enclustra Mars-ZX2 Zynq 7010 board. I would like to test SG DMA feature with a stream pattern generator.

I implemented a design with axidma IP and I designed a simple axi stream test pattern generator. I downloaded axaxidma_example_sg_intr example software from Xilinx. The design mostly works, but I cannot get an IOC interrupt.

Vivado and SDK version are 2018.1.

If I do not use packets in the stream, the dma engine works fine until processes all block descriptors then stops. It is OK, the software should set new descriptors in the interrupt routine, but the interrupt never happens. The dma engine fills the block descriptor with the appropriate data: "completed" bit, and number of transfered bytes.

If I use packets in the stream (tlast = '1' at the last data write), the dma engine does neither fill the block descriptor, nor generates IOC interrupt.

All the 3 interrupts (IOC, Delay, Error) are enabled - I read back the CR register. The axidma/introut pin is connected, because delay interrupt is asserted after the last packet ends and the preprogrammed time expired. But IOC interrupt is never asserted, though I tried everything I could devise.

 

Any idea what can go wrong?

 

Laszlo

 


Accepted Solutions
Visitor
Posts: 3
Registered: ‎05-15-2018

Re: Axidma IOC interrupt is not asserted in SG mode

Hi,

 

After intensive debugging with ILA core, I solved the problem. When I customized the axi_dma IP into my design, I did not disable Command/Status Stream interface (default is enabled). So when a stream packet arrived, the logic waited for status stream information, which never arrived. Neither did IOC interrupt. I recustomized the axi_dma, and now IOC interrupt works.

 

Laszlo

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Xilinx Employee
Posts: 112
Registered: ‎10-04-2016

Re: Axidma IOC interrupt is not asserted in SG mode

Hi @laczol23,

It sounds like you are doing a stream to memory map transfer. 

 

What is IRQThreshold set to in the S2MM_DMACR register? How many interrupts does the IRQThresholdSts register report in S2MM_DMASR? An interrupt is only sent to the processor when IRQThreshold events occur. 

 

Another area to look is in the protocol of the AXI Stream interface. Do you have a trace of the output of your test pattern generator?

 

Regards,

 

Deanna

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Visitor
Posts: 3
Registered: ‎05-15-2018

Re: Axidma IOC interrupt is not asserted in SG mode

[ Edited ]

 Hi Deanna,

 

Yes, I am doing only a stream to memory map transfer.

I set IRQThreshold to 1, to get interrupt on every packet. Status register does not report any interrupt.

I did some debugging with ILA core.

I attached some screenshots.

Packet length here means the packet length set in the sg block descriptor. I used 256 bytes as packet length. Tlast can be set on the pattern generator. 1024 means that the pattern generator asserts tlast at the 1024th byte (256th transfer). I set up 8 block descriptors, so the 4 transfer will not run out of descriptors. The *_bd_8.jpg screenshots show the block descriptors after the dma process. 

The axidma_packet_256_tlast_1024.jpg screenshot shows that the transfer was executed, but the axidma_packet_256_tlast_1024_bd_8.jpg screenshot shows that the "transfer completed" bit in the 4th block descriptor was not asserted, and the transfered bytes field was not filled. And no interrupt was asserted.

When I set tlast to 1028, it means that all 4 block descriptors will be completed.

You can see it on axidma_packet_256_tlast_1028.jpg, and axidma_packet_256_tlast_1028_bd_8.jpg. In the latter you can see, that all 4 block transfers were completed.

I attached axidma_packet_256_tlast_512_delay_it.jpg screenshot too. Delay threshold was set to 3. You can see that a delay interrupt is asserted after the preprogrammed delay passed. Delay IT is generated only if I generate tlast at the end of a packet.

Tstvec[3:2] signals are eof (end of frame) and sof (start of frame). 

 

Best regards,

Laszlo

axidma_packet_256_tlast_1024.jpg
axidma_packet_256_tlast_1024_bd_8.jpg
axidma_packet_256_tlast_1028.jpg
axidma_packet_256_tlast_1028_bd8.jpg
axidma_packet_256_tlast_512_delay_it.jpg
Visitor
Posts: 3
Registered: ‎05-15-2018

Re: Axidma IOC interrupt is not asserted in SG mode

Hi,

 

After intensive debugging with ILA core, I solved the problem. When I customized the axi_dma IP into my design, I did not disable Command/Status Stream interface (default is enabled). So when a stream packet arrived, the logic waited for status stream information, which never arrived. Neither did IOC interrupt. I recustomized the axi_dma, and now IOC interrupt works.

 

Laszlo