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Axidma IOC interrupt is not asserted in SG mode

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Posts: 1
Registered: ‎05-15-2018

Axidma IOC interrupt is not asserted in SG mode

Hi,

 

I am experimenting with an Enclustra Mars-ZX2 Zynq 7010 board. I would like to test SG DMA feature with a stream pattern generator.

I implemented a design with axidma IP and I designed a simple axi stream test pattern generator. I downloaded axaxidma_example_sg_intr example software from Xilinx. The design mostly works, but I cannot get an IOC interrupt.

Vivado and SDK version are 2018.1.

If I do not use packets in the stream, the dma engine works fine until processes all block descriptors then stops. It is OK, the software should set new descriptors in the interrupt routine, but the interrupt never happens. The dma engine fills the block descriptor with the appropriate data: "completed" bit, and number of transfered bytes.

If I use packets in the stream (tlast = '1' at the last data write), the dma engine does neither fill the block descriptor, nor generates IOC interrupt.

All the 3 interrupts (IOC, Delay, Error) are enabled - I read back the CR register. The axidma/introut pin is connected, because delay interrupt is asserted after the last packet ends and the preprogrammed time expired. But IOC interrupt is never asserted, though I tried everything I could devise.

 

Any idea what can go wrong?

 

Laszlo

 

Xilinx Employee
Posts: 54
Registered: ‎10-04-2016

Re: Axidma IOC interrupt is not asserted in SG mode

Hi @laczol23,

It sounds like you are doing a stream to memory map transfer. 

 

What is IRQThreshold set to in the S2MM_DMACR register? How many interrupts does the IRQThresholdSts register report in S2MM_DMASR? An interrupt is only sent to the processor when IRQThreshold events occur. 

 

Another area to look is in the protocol of the AXI Stream interface. Do you have a trace of the output of your test pattern generator?

 

Regards,

 

Deanna

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