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Visitor vascuen
Registered: ‎06-07-2019

Can AXI DMA MM2S tlast signal be asserted each ~32K words?

Hello everyone,

First of all, I am using VIVADO 2016.2.

I am working on a design which includes a custom IP core that has as input an AXI4-Stream Interface. This interface expects to receive transactions of 2^15 words with a size of 4B per word. At the entrance of this IP core there is connected an AXI DMA. The DMA is working fine (at least seems so), but it is asserting the tlast signal each 64 words. My questions are:

  1. Is it possible to configure the AXI DMA transfer size to 2^15 instead of 64?
  2. In case it is, how should I do it?

Thank you in advance.

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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: Can AXI DMA MM2S tlast signal be asserted each ~32K words?

Hi @vascuen ,

I am assuming that your AXI DMA hardware is opperating in Scatter Gather mode. 

Please refer to PG021. The MM2S_Control field in the Buffer Descriptor has bits to control your start of frame and end of frame. You need to adjust when end of frame is set to cover your 128kB packet. The setting of end of frame corresponds to the assertion of TLAST.




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