05-19-2018 01:09 PM
I'm using Vivado 2017.1 or 2018.1.
Is there some flavor of existing IP that will do this already, or can I get inside and hack one to make it do it?
I'd like to have a UART with an AXI control interface, for doing things such as setting baud rate and number of bits. However, rather than the serial data also going through AXI, I'd like separate native FIFO connections that go elsewhere on my FPGA. When I look at the datasheet for AXI UART 16550 v2.0 (PG143), Figure 1-1 shows a diagram that I can hack in my mind's eye. But can I do this for real, and above board of course?
05-21-2018 06:44 AM
This is true, @satguy . In fact, I already have my own code I could hack. But I feel like hacking an AXI UART will give my code more longevity. For example, if AXI were upgraded in the future, I could take the existing hack work and reapply it to the upgraded baseline.
05-21-2018 08:21 AM
05-21-2018 08:36 AM
Note I've been doing hardware and software for 43 years, now 3.5 years on Xilinx FPGAs. My gut correctly suggests I do what I'm trying to do. (I won't engage any further.)
05-21-2018 10:51 AM
05-21-2018 11:19 AM
No permanent offense. I would still like to base on existing AXI UART rather than my own. Other aspects are code maturity and unknown bugs in mine, no matter how simple the concept.
Enough for now. I have other software demons to conquer...
05-21-2018 01:26 PM
Create the IP, expand the code. If none of it is encrypted, write a script to generate the IP you want, and another script (say perl) to automatically modify it in the way you want.
Or you could do it manually. But if anything ever changes on a future release, you'll wish you had done it via script.
On the other hand, if you do it by script, the change may also break your script.
05-23-2018 12:36 PM
Why not create something that takes data from an AXI-Stream and writes to the AXI-lite and vice-versa and place that in front of the AXI-UART? Requires no hacking existing IP and will stay correct after an IP-upgrade.
05-23-2018 01:01 PM
I think what you're saying, @vanmierlo , is to have this created thing read the AXI-UART on the AXI end (I would call that "behind", not in "front"). This thing must read individual characters, and then send them back into a different AXI. That's a lot of char-banging and a lot of effort, probably more than using my existing one I'd rather not use and dealing with future bugs. That's also a big bug magnet. Sorry, I don't like that idea at all, as I understand you to mean...
05-24-2018 02:29 AM
When you talk about reading, I agree it looks more like behind. I started with writing which places the AXIS->AXIlite converter in front :-) In the end it really depends on what side you're looking at.
I only presented you with an idea. Whether you like it or not is entirely up to you. No need to feel sorry.