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Explorer
Explorer
9,985 Views
Registered: ‎02-05-2015

Connect Axi DMA to multiple inputs

I have a Vivado HLS block which accepts 5 input streams like so:

void top_function(hls::stream<AXI_VALUE> &in_stream_fuel,
            hls::stream<AXI_VALUE> &in_stream_reachability,
            hls::stream<AXI_VALUE> &in_stream_slope,
            hls::stream<AXI_VALUE> &in_stream_shadow,
            hls::stream<AXI_VALUE> &in_stream_texture,
            hls::stream<AXI_VALUE> &out_stream){
#pragma HLS RESOURCE variable=out_stream core=AXI4Stream metadata="-bus_bundle OUTPUT_STREAM"
#pragma HLS RESOURCE variable=return core=AXI4LiteS
#pragma HLS RESOURCE variable=in_stream_fuel core=AXI4Stream metadata="-bus_bundle STREAM_FUEL"
#pragma HLS RESOURCE variable=in_stream_reachability core=AXI4Stream metadata="-bus_bundle STREAM_REACHABILTY"
#pragma HLS RESOURCE variable=in_stream_slope core=AXI4Stream metadata="-bus_bundle STREAM_SLOPE"
#pragma HLS RESOURCE variable=in_stream_shadow core=AXI4Stream metadata="-bus_bundle STREAM_SHADOW"
#pragma HLS RESOURCE variable=in_stream_texture core=AXI4Stream metadata="-bus_bundle STREAM_TEXTURE" 
...
//code here
...
}

I have another block which first normalizes and outputs to DDR memory five 512x512 matrices and now with this block I want to aggregate those 5 maps into one, by reading each map in sub-matrices of 32x32.

 

The reason why I need 5 input streams and not only one is that in memory the five 512x512 matrices are contiguous and so I need to have 5 pointers to 5 different locations.

 

The only way I know of connecting the streams with DDR memory is the Axi DMA block but for all I know I can just connect one of them to each input stream, so I would need 5 Axi DMA blocks to do this, which is a lot in terms of resources.

 

Is there a way of using the same Axi DMA for the 5 inputs?

Also, is there a better way of doing this?

 

Thank you in advance for the help

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11 Replies
Xilinx Employee
Xilinx Employee
9,968 Views
Registered: ‎08-01-2008

Re: Connect Axi DMA to multiple inputs

Check this example design

http://www.xilinx.com/support/answers/59532.html
Thanks and Regards
Balkrishan
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Explorer
Explorer
9,930 Views
Registered: ‎02-05-2015

Re: Connect Axi DMA to multiple inputs

Ty for the answer. I was reading that example for the last couple of hours and I still don't know how to adapt it to my design and even if that is possible.

 

That's a very difficult example to understand...

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Explorer
Explorer
9,925 Views
Registered: ‎02-05-2015

Re: Connect Axi DMA to multiple inputs

Is Multichannel with scatter gather mode a solution to my problem also?
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Xilinx Employee
Xilinx Employee
9,889 Views
Registered: ‎08-02-2011

Re: Connect Axi DMA to multiple inputs

Hello again jmales,

 

Is Multichannel with scatter gather mode a solution to my problem also?

It could work, but multichannel mode interleaves all channels onto one single AXI Stream interface. So the bus is time-shared among all channels. This will affect your overall latency. Based on our past discussions, I'm guessing this isn't what you want.

www.xilinx.com
Explorer
Explorer
9,868 Views
Registered: ‎02-05-2015

Re: Connect Axi DMA to multiple inputs

Yes, I was also thinking about that after watching some SG videos.

 

So @bwiec, do you also recommend the method @balkris said?

 

I don't know if I'm explaining it very well, since it's difficult but what I want is this:

 

In DDR I have the maps organized like so:

[map1:512x512][map2:512x512][map3:512x512]

 

and I want a block that takes 32x32 of each map (that's why I have 5 input streams) and aggregates them into one.

 

Since the 32x32*5 data isn't contigous I can't just use a simple Axi DMA correct? Will the solution @balkris provided solve this problem?

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Xilinx Employee
Xilinx Employee
9,863 Views
Registered: ‎08-02-2011

Re: Connect Axi DMA to multiple inputs

Since the 32x32*5 data isn't contigous I can't just use a simple Axi DMA correct?

Well your 32x32 is contiguous, right? To use simple-mode DMA, you'd need to configure it for each 32x32 section and do that 5 times to get all 5 streams.

 

In your case SG might make sense because each BD could describe one 32x32 block and you would construct a BD ring of length 5 to get all 5 streams. This being the case, though, you wouldn't get all 5 blocks in parallel. You'd get one 32x32 block at a time.

 

SG with the AXI DMA has the additional advantage that the core will pre-fetch BDs so memory accesses will be more pipelined and so higher performance.

 

I'm not super familiar with the design that balkris mentioned, but taking a brief look, it's a very simplified DMA with no scatter gather that just implements a ping-pong buffer. If you decide to go the route of 5 parallel DMAs and you can statically allocate buffers for your DMA, then this might be a good route to go because I think it's probably very small and zero CPU overhead compared to AXI DMA.

 

 

www.xilinx.com
Explorer
Explorer
9,813 Views
Registered: ‎02-05-2015

Re: Connect Axi DMA to multiple inputs

In your case SG might make sense because each BD could describe one 32x32 block and you would construct a BD ring of length 5 to get all 5 streams. This being the case, though, you wouldn't get all 5 blocks in parallel. You'd get one 32x32 block at a time.

Ah ok.. I thought I would get it in parallel or get the 5 streams as one stream of size 32x32x5. In that case I think Simple DMA is better for me, since I know almost nothing about SG.

 

Well, since both you guys recommend the ping-pong buffers, I will look again at that and try to understand how to do that in my design.

 

@bwiec Though, I wanna ask you this: how would you do this if it was your project?

 

Also, do you know of any way I can get the 5 32x32 matrices to enter in parallel?

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Explorer
Explorer
9,597 Views
Registered: ‎02-05-2015

Re: Connect Axi DMA to multiple inputs

@balkris I've looked again at the example you suggested but I have some doubts which I hope you can help me with.

 

1-I still need to use an AXI DMA correct?

 

2-If I need to send 5 buffers of size 512 bytes to the same function how do I do that with the pingpong buffers? From what I'm understanding I need to call stream2pingpong 5 times correct? How is that better than my previous "solution"?

 

3-The stream to ping (i.e. the MM to stream) is done when the AXI_MASTER is defined. How is this going to be done when I pass the block to Vivado and then to SDK? In the last will I be able to pass from inputs (stream2ping) to outputs (stream2pong) whenever I want? I'm really confused about this.

 

Thnak you in advance.

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Newbie eroxyde
Newbie
1,309 Views
Registered: ‎06-28-2018

Re: Connect Axi DMA to multiple inputs

Hi everyone !

In the AR# 59532 page, the link for the stream2pingPong.h file is broken ?

I have an interest for that example!

 

Eric

 

Thanks ! :)

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Visitor hamidnaghi
Visitor
622 Views
Registered: ‎03-12-2018

Re: Connect Axi DMA to multiple inputs

I could build that HLS IP and import it to VIVADO but how we can design the block diagram and implement the SDK? Is there any .tcl for that example and the related SDK code?

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Xilinx Employee
Xilinx Employee
454 Views
Registered: ‎10-04-2016

Re: Connect Axi DMA to multiple inputs

Hi @hamidnaghi,

Would you please start a new post with your question? I'm not sure what you are asking or how it relates to the original thread.

Regards,

Deanna

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