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Visitor arcolima
Visitor
159 Views
Registered: ‎07-05-2018

Custom AXI IP address blocks not exported to SDK

Hello,  

I am designing a custom video IP in VIvado 2018.1.  

I packaged my VIDEO_IP, generated from a block design that includes 7 sub-IPs: some are Vivado Catalog cores, some are custom written IPs. 

I defined an address block for each sub-IP, and with address editor I mapped the blocks in the external slave S_AXI, as follows:  

External Masters

     

S_AXI (16 address bits : 0x0000 [ 64K ])

     

G_BRIDGE

S_AXI_LITE

Reg

0x3000

4K

0x3FFF

S_BRIDGE

S_AXI_LITE

Reg

0x4000

4K

0x4FFF

TPG

axi_lite_ctrl

Reg0

0x5000

4K

0x5FFF

LUT_0

s_LUT_axi

Mem0

0x1000

4K

0x1FFF

LUT_1

s_LUT_axi

Mem0

0x2000

4K

0x2FFF

reg_space_0

s00_axi

reg0

0x0000

4K

0x0FFF

v_mix_0

s_axi_CTRL

Reg

0x8000

8K

0x9FFF

When exporting this project to SDK, only the address block at the highest offset (V_MIX in this case) is mapped and can be accessed, all the other block are unreachable,  

The reason is that in the base_zynq_design.hwh file exported by Vivado, the VIDEO_IP peripheral's address space is defined by C_BASEADDR and C_HIGHADDR that always match the values of the highest address block  

.... 

<PARAMETER NAME="Component_Name" VALUE="base_zynq_design_VIDEO_IP_0_0"/> 

<PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/> 

<PARAMETER NAME="C_BASEADDR" VALUE="0x40028000"/> 

<PARAMETER NAME="C_HIGHADDR" VALUE="0x40029FFF"/> 

</PARAMETERS> 

Why is the peripheral's address space reduced to the highest block only? What am I missing? Any suggestion?

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Xilinx Employee
Xilinx Employee
147 Views
Registered: ‎10-30-2017

Re: Custom AXI IP address blocks not exported to SDK

Hi @arcolima,

Please check this AR: https://www.xilinx.com/support/answers/66322.html

Best Regards,
Srikanth
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