We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor toniohabets
Registered: ‎05-24-2018

Error at MIG and DMAs in Vivado 2018.2 version

I have a problem regarding DMA in the 2018.2 version of Vivado. In our design (ZYNQ 7z035) we have (beside the standard PS DDR memory) a local PL DDR memory. We want to transfer data from PS domain into the PL DDR domain. This fails and it seems that the DMA and/or MIG hangs. Some details: We have made a separate toplevel template for debugging the DMA + MIG combination. We also made a trace with an ILA core. I see that the DMA starts 3 burst transfers (16 transfers per burst) to DDR. The first burst is ok. The second burst stops after the first transfer (WREADY from MIG goes low) and at that point the MIG and DMA hang… Do you see a similar behavior? We have no idea yet how to solve the issue. Can you help us? Are there known issues with the DMA in 2018.2 version? Attached a screenshot of ILA trace and also a snippet of the DMA vivado design. Thanks for your help. Tonio
0 Kudos
2 Replies
Registered: ‎11-28-2016

Re: Error at MIG and DMAs in Vivado 2018.2 version

Hello @toniohabets,

Typically issues with AXI DMA are usually related to configuration and application problems so I'm going to move this to the AXI Infrastructure community so those experts can take a look.

0 Kudos
Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: Error at MIG and DMAs in Vivado 2018.2 version

Hi @toniohabets,

Rather than trying to resolve this issue, my first recommendation is that you remove the two AXI DMA IPs and instead use a single AXI CDMA.

The AXI CDMA is the appropriate DMA for memory to memory transfers like you are doing here. Using two AXI DMAs introduces a lot of unnecessary conversions (AXI memory mapped to AXI stream to AXI memory mapped), increases complexity and reduces performance.




Don’t forget to reply, kudo, and accept as solution.