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Adventurer
Adventurer
574 Views
Registered: ‎08-10-2017

Generating AXI Signals

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I have block design containing several Block RAMs and 7 series MIG for DDR3. All are interconnected using AXI protocol.

 

 

I studied AXI Master Burst (https://www.xilinx.com/support/documentation/ip_documentation/axi_master_burst/v2_0/pg162-axi-master-burst.pdf) and implemented a state machine for generating AXI signals, but after Synthesis, I noticed many signals in axi_master_burst are removed (got this warning : Unused Sequential element was removed).

 

 

Should I use DONT_TOUCH attribute for each and every signal that is being removed ?
If there is a better and easier way to generate AXI master signals, please tell me where to start..

 

I'm using Vivado 2017.2 and Ubuntu 16.04

 

[Synth 8-6014] Unused sequential element sig_stat_tag_reg_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":17757]

[Synth 8-6014] Unused sequential element sig_pop_status_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":17337]

[Synth 8-6014] Unused sequential element GEN_OFFSET_MODE.strt_offset_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":951]

[Synth 8-6014] Unused sequential element GEN_OFFSET_MODE.end_offset_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":966]

[Synth 8-6014] Unused sequential element GEN_OFFSET_MODE.sig_strb_value_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":911]

[Synth 8-6014] Unused sequential element GEN_ADDR_MODE.strt_offset_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":1086]

[Synth 8-6014] Unused sequential element GEN_ADDR_MODE.end_offset_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":1102]

[Synth 8-6014] Unused sequential element GEN_ADDR_MODE.sig_strb_value_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":1043]

[Synth 8-6014] Unused sequential element sig_input_reg_full_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":10837]

[Synth 8-6014] Unused sequential element sig_xfer_reg_full_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":11137]

[Synth 8-6014] Unused sequential element sig_next_tag_reg_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":13608]

[Synth 8-6014] Unused sequential element sig_next_cmd_cmplt_reg_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":13613]

[Synth 8-6014] Unused sequential element sig_next_dre_src_align_reg_reg was removed.  ["/media/cn1lab005/dataFYP/vivado_projects/fyp/bfm_test/bfm_test.srcs/sources_1/bd/design_1/ipshared/e744/imports/hdl/axi_master_burst_v2_0_vh_rfs.vhd":9385]
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and many more like that..

  

Thank You

 

Jagannath

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1 Solution

Accepted Solutions
Scholar austin
Scholar
704 Views
Registered: ‎02-27-2008

Re: Generating AXI Signals

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j,

 

Yes, if not all features of the IP are used, trimming occurs.  No problem.  Again, you need to verify your design does what you want.  A bug in your code may lead to the trimming, and cause problems.  So the trimming per se isn't good, or bad.  It just lets you know stuff was removed.  It is always up to you to verify your design.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
3 Replies
Scholar austin
Scholar
514 Views
Registered: ‎02-27-2008

Re: Generating AXI Signals

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J,

 

If it isn't used, why keep it?  Trimming unused logic from designs is a good thing.  Discovering why it is unused means you get to be a better designer.

 

So rather than fight to keep something of no value, I would go discover WHY it has no value.  Perhaps you design has problems.

Austin Lesea
Principal Engineer
Xilinx San Jose
Adventurer
Adventurer
501 Views
Registered: ‎08-10-2017

Re: Generating AXI Signals

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@austin

 

Thanks for replying Austin.

 

I agree that trimming unused logic is a good thing.

What has me worried is that the elements removed are from Xilinx IP axi_master_burst_v2_0 (from <vivado_install_path>/data/ip/xilinx). And if these sequential elements are removed, would AXI signals be generated properly ?

 

 

Regards

Jagannath

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Scholar austin
Scholar
705 Views
Registered: ‎02-27-2008

Re: Generating AXI Signals

Jump to solution

j,

 

Yes, if not all features of the IP are used, trimming occurs.  No problem.  Again, you need to verify your design does what you want.  A bug in your code may lead to the trimming, and cause problems.  So the trimming per se isn't good, or bad.  It just lets you know stuff was removed.  It is always up to you to verify your design.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose