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Registered: ‎10-24-2018

HPC port Coherency on Linux

Hi, I'm trying to make coherent DMA transfers using the HPC port and a CDMA as master, on Linux. The transfers do not appear as coherent. What am I missing? has anyone managed to make this work on Linux alongside the SMMU? I also read these 2 posts.
https://www.xilinx.com/support/answers/69446.html

https://forums.xilinx.com/t5/Embedded-Linux/Zynq-Ultrascale-HPC-ports/td-p/798011
What I am doing so far:

-Hardwiring the AxCache and AxProt bits of the HPC port to 0b1011 and 0b11 respectively.

-Writing to the LPD_SLCR register in order to enable broadcast of outer-shareable transactions

-Writing to the Shareable_Override_register in order to mark these transactions shareable in the CCI

-Inserting to a SMR register of the SMMU a translation of my choice.

-Marking the page table entries in Linux as outer shareable with proper bit manipulation.

Do I miss anything?

Thanks in advance.

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Xilinx Employee
Xilinx Employee
592 Views
Registered: ‎10-04-2016

Re: HPC port Coherency on Linux

Hi @ysterioustranger,

We have two references on the Wiki that you should take a look at.

 

Coherency with the HPC ports

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Coherency

 

SMMU configuration

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841981/Zynq+UltraScale+MPSOC+SMMU

 

You might need to set AxPROT to 3'b010. I suspect marking the transaction as privileged would prevent cache hits if you are just running Linux.

 

Regards,

 

Deanna

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