04-21-2015 09:29 AM
The AXI Reference Guide (UG761) states:
"AXI4 is for memory mapped interfaces and allows burst of up to 256 data transfer
cycles with just a single address phase."
My question is: How do I initiate a burst in software? Do I use memcpy() in C and a burst transfer is performed on the AXI bus? I've search online for an answer to this with no success.
04-21-2015 10:59 AM
04-21-2015 11:14 AM
Bursts from a CPU are generally only issued by cache and related CPU hardware. So the short answer is to set the your MMU/translation table to be "normal" memory (versus peripheral or device memory), and then enable the cache. When the cache either fetches or evicts a cacheline, a burst will occur. Note that this also means that it is up to the CPU application to perform cache maintainance operations if the data must be moved out to the PL in a timely manner.
04-23-2015 08:07 AM
I've tried doing that to an AXI peripheral in PL with the ldm and stm instrustions a while ago. I was able to generate burst read of 4 beats and burst write of 2 beats at most, even though I tried to read/write more registers. This was observed on hardware with Vivado logic analyzer. I was unable to generate longer burst to my AXI peripheral with software. Also, note that I was trying to burst to an AXI peripheral in PL, therefore I believe it doesn't involve any cache operation. Bursting to / from DRAM with software is another story, I don't think there is a way to force that.
04-23-2015 10:19 AM
The L2 cache controller has a 32-byte cache line. So the maximum you would usually expect to see at a 32-bit interface is a burst of 8 beats (there is a double cacheline mode for prefetching, but let's ignore that for now).
There is no difference from the CPU perspective of the PL and DRAM. It is all about how the MMU translation tables are configured.
See this Answer Record for how to mark the PL to be normal memory:
12-27-2017 11:39 AM
It stands for Programmable Logic. In Zynq chips there is Processor Subsystem and PL.
02-20-2018 10:18 AM