04-03-2018 05:10 PM
I'd like to execute post synthesis functional simulation with AXI VIP and ZYNQ VIP by xsim.
Of cause I already have executed RTL functional simulation with AXI VIP and ZYNQ VIP by xsim and got the result as fine.
However I switched simulation mode from RTL to post synthesis functional simulation and got the result as failed.
According to log file, it seems that it could not use these VIP under netlist simulation.
How do I execute post synthesis functional simulation with AXI VIP and ZYNQ VIP by xsim ?
I have an idea to resolve it by force command. But I don't use "force" command...
Design : VerilogHDL and VHDL mixed simulation (RTL)
04-06-2018 08:27 AM
The AXI VIP and Zynq VIP synthesize to wires, so they are not available for post-synthesis functional simulation.
Depending on what you are trying to simulate, you might be able to instantiate the AXI VIP in your test bench, connect it to your DUT and insert AXI transactions that way.
04-09-2018 03:49 AM
Thank you for your reply.
My purpose is to understand video timing controller by Xilinx (especially generator function) with AXI VIP and ZYNQ VIP.
I can NOT read this RTL design. So, I'd like to do post-synthesis functional simulation with AXI VIP and ZYNQ VIP.
Do you have any idea to resolve my issue ?
I'd like to know the meaning of each parameter and behavior of video timing controller (generator).