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Scholar watari
Scholar
391 Views
Registered: ‎06-16-2013

How do I execute post synthesis functional simulation with AXI VIP and ZYNQ VIP by xsim ?

Hi all

 

I'd like to execute post synthesis functional simulation with AXI VIP and ZYNQ VIP by xsim.

Of cause I already have executed RTL functional simulation with AXI VIP and ZYNQ VIP by xsim and got the result as fine.

However I switched simulation mode from RTL to post synthesis functional simulation and got the result as failed.

According to log file, it seems that it could not use these VIP under netlist simulation.

How do I execute post synthesis functional simulation with AXI VIP and ZYNQ VIP by xsim ?

 

I have an idea to resolve it by force command. But I don't use "force" command...

 

[My environment]

Vivado 2017.4

Design : VerilogHDL and VHDL mixed simulation (RTL)

Device: XC7Z020CLG484-1

 

Best regards,

Best regards,

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2 Replies
Xilinx Employee
Xilinx Employee
349 Views
Registered: ‎10-04-2016

Re: How do I execute post synthesis functional simulation with AXI VIP and ZYNQ VIP by xsim ?

Hi @watari,

The AXI VIP and Zynq VIP synthesize to wires, so they are not available for post-synthesis functional simulation. 

 

Depending on what you are trying to simulate, you might be able to instantiate the AXI VIP in your test bench, connect it to your DUT and insert AXI transactions that way.

 

Regards,

 

Deanna

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Scholar watari
Scholar
336 Views
Registered: ‎06-16-2013

Re: How do I execute post synthesis functional simulation with AXI VIP and ZYNQ VIP by xsim ?

Hi @demarco

 

Thank you for your reply.

 

Got it.

My purpose is to understand video timing controller by Xilinx (especially generator function) with AXI VIP and ZYNQ VIP.

I can NOT read this RTL design. So, I'd like to do post-synthesis functional simulation with AXI VIP and ZYNQ VIP.

 

Do you have any idea to resolve my issue ?

 

*)

I'd like to know the meaning of each parameter and behavior of video timing controller (generator).

 

Best regards,

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