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Observer p.hayk
Registered: ‎11-21-2013

How to make ACLK centric data transfer

In the AXIS stream speck the ACLK is defined as:

The global clock signal. All signals are sampled on the rising edge of ACLK.

Which means that it is assumed that AXIS master and slave are receiving the same ACLK. Can you please help understand following:
1) If there is a ACLK slew on AXIS master and slave blocks,it is left under designer responsibility. Speck does not set any limitation on that. Is my understanding right?
2) The data transfer should be ACLK center aligned. So the developer should make the AXIS master to send clock center aligned data. Right?
3) How to make ACLK centric data transfer? Imagine you have global clock in the whole system, to make data to be transferred clock center aligned to that data, you need to generate new clock which has phase left shifted from your global clock. Any ideas how we can do it in FPGA?

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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: How to make ACLK centric data transfer

Hi @p.hayk,

If you are creating your own AXI-Stream IP, I would recommend starting from the templates in the Create and Package IP Wizard. That should avoid the issues with ACLK skew you are poking at.


Chapter 3 of UG1118 covers how to generate this template. 






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