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513 Views
Registered: ‎04-26-2017

How to take advantage of two AXI_GP in the Zynq?

Hello. I was wondering about the titlle of my post. I understand why to have one master and one slave AXI_GP, but why two of each one? Some ideas that I have:
* To use one of them in each A9 core?
* To have more addresses if needed?
Can I take some advantage to use the both masters or slaves in the same core? Any example?

 

Thanks

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6 Replies
470 Views
Registered: ‎04-26-2017

Re: How to take advantage of two AXI_GP in the Zynq?

No ideas? Maybe also could be useful for example with FreeRTos, to "speak" with 2 slaves at same time in different tasks? I read the AXI section of the Zynq's TRM and the AXI reference guide and I have no response for this question.

 

Regards

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-26-2014

Re: How to take advantage of two AXI_GP in the Zynq?

Hi,

 

I know, I'm not answering your question to the point, but there are some points to be understood.

1. AXI_GP, AXI_HP and others are AXI ports of A9 processor, they are ports of PS (processing system). PS has processors and many peripheral connected by AXI interconnects.

 

2. About FreeRToS tasks accessing 2 slaves at a time: they may not be real parallel, just pseudo parallel. Treads become real parallel when they run on different cores. OK, lets assume that they are running on two different cores, then it is possible that they communicate with 2 slaves in parallel.

 

Regards,

Ravi

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456 Views
Registered: ‎04-26-2017

Re: How to take advantage of two AXI_GP in the Zynq?

1. AXI_GP, AXI_HP and others are AXI ports of A9 processor, they are ports of PS (processing system). PS has processors and many peripheral connected by AXI interconnects.

 

Yes I know. The thing is to know why are they present as 2 master and 2 slaves and how can I take an advantage from that (I suppose that there are advantages to have two, or why are they there?).

 

Regards

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Xilinx Employee
Xilinx Employee
436 Views
Registered: ‎02-26-2014

Re: How to take advantage of two AXI_GP in the Zynq?

Hi,

 

1. multiple master interfaces: to these slaves in PL can be connected. With multiple ports, we get multiple address ranges, like address ranges for M_AXI_GP0 and M_AXI_GP1. Single address range, with single port is also possible, two ports gives chance communicate with two different slaves in PL at a time, may be by different masters in PS. This will lead to other advantages like possibility of using different frequencies with each port, may be some more....

 

2. multiple slave interfaces: The reason is different here. There are different slave ports, S_AXI_HP ports directly go to DDR controller and also can access OCM. ACP port going to snoop controller, and slave GP ports connected to peripherals.

If there are multiple masters in PL accessing DDR, it is good to make use of multiple ports, instead of using single HP port using an interconnect, as it may offer better bandwidth.

 

Regards,

Ravi

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430 Views
Registered: ‎04-26-2017

Re: How to take advantage of two AXI_GP in the Zynq?

Ok. I saw that with only a Master AXI_GP, the addressable range is 0x4000_000 to 0x7FFF_FFFF. Adding the Master AXI_GP 2, it is extended from 0x8000_000 to 0xBFFF_FFFF.

 

My doubts now are:

* How to use both Master AXI_GP at same time? One from each A9 core? From different task in for example FreeRToS?

* How to do write and read operations at same time? It is possible? Yes according AXI spec but what about the Double A9 implementation used by the Zynq?

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-26-2014

Re: How to take advantage of two AXI_GP in the Zynq?

Hi,

 

Have a look at the Figure-5-1 in Zynq 700 TRM.

In this diagram all the interconnects are explained, and you can see M_AXI_GP ports connected to PL.

 

   -  All bare metal applications use only one core, only operating systems like linux use multiple cores. This means that, using bare metal application you can never perform multiple AXI transfers at a time. You may have two applications running on each core, and may generate parallel AXI transfers.

 

- Have a look at SCU interconnect in the diagram, all the transfers generated by A9 cores will go to this interconnect. If the transfers are to M0, and M1, then parallel transfers are possible. But if both the transfers are to M0, they may get executed in sequence. 

 

Regards,

Ravi

 

Regards,

Ravi

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