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Observer stu2k@msn.com
Observer
1,039 Views
Registered: ‎11-22-2014

How to test AXI4-stream custom IP with master interface

I am trying to develop my first AXI4-stream custom IP with master interface.  The IP is essentially a sample generator, and I have implemented it by creating a simple counter that increments by 3 whenever tready is high.  A sample is a 32-bit value and is generated if the counter has produced a number divisible by 4, thus tvalid is the same as tlast, and both being equal to ~|counter[1:0].  The tdata is the 32-bit value of the counter.

 

I have created this IP and packaged it.  While still in the IP-packager instance of Vivado, I cut and paste the code into another instance of Vivado where I instantiate the IP in a testbench.  Right now the testbench drives the clock, resetn and tready.  I have observed the output tdata, tvalid and tlast signals to be what I expect, with the only exception being that I happen to drive tready high on the negative edge of the clock, so tvalid and tlast are only high for half of a clock width.  That problem should clear itself once I align that signal being asserted with a positive edge clock signal, although I might need to tie those signals to the posedge transition via a latch.  (I'm not certain if this is required for the IP to meet the AXI4-stream interface standards.)

 

Is there a standard testbench that goes through the expected/required signal transitions that I should be testing my custom IP against?  I briefly looked at the AXI Validation IP, but I am more concerned with how to simulate the circuit to personally validate the results.  Also, creating my own testbench is helping me gain a better understanding of how the AXI4-stream protocol works.

 

I have implemented the design into a system utilizing an AXI DMA module with mixed results on my Zedboard.  I am using the standard loop back AXI DMA example, which I have validated its operation.  I then replaced the MM2S -> S2MM connection with the output of my sample generator.  Now when I read 512 32-bit values from the receive buffer I only get 1 valid sample.  On top of that, the first sample I get has the value of 48 instead of the expected 0.  When I flush the cache again and perform another read I get the value 60, the next expected value, along with 511 other non-expected values.  Repeating this process again and I get the expected value of 72 with the other non-expected values.  I am getting these results regardless if I am using an AXI4-stream FIFO to feed the S2MM interface on the AXI DMA module.  I am a little confused as to why I am not getting more samples, as well as why sample 0, 12, 24 and 36 are lost.

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3 Replies
Moderator
Moderator
1,004 Views
Registered: ‎11-09-2015

Re: How to test AXI4-stream custom IP with master interface

Hi stu2k@msn.com,

 

You should look again at the VIP. I think this is what you need as it includes a protocol checker (i.e. it will tell you if your interface is not following the AXI spec).

 

Also note that vivado can generate a template for AXI4 interface. This is usually helpful to have a quick functionnal AXI4 interface.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer stu2k@msn.com
Observer
997 Views
Registered: ‎11-22-2014

Re: How to test AXI4-stream custom IP with master interface

Florent,

 

I'll take another look at the VIP.  Unfortunately my problem with AXI4-Stream is understanding the files Vivado creates for it.  I see a top level file and then a separate file for each master or slave interface that you specified.  I see areas where I can insert user code, but I'm getting a little confused on how my user code can become tdata, tvalid, etc.

 

Is there a user guide or anything else that tells me what the generated code does and how I can insert my own code into it?  It feels like the top level file needs to instantiate the module in the master interface, and I can customize what the master interface does.  However, right now it feels like I am stuck trying to look at the RTL schematic of the master interface to essentially reverse engineer what it is doing prior to figuring out how to customize is it.

 

Thanks,

 

Stuart

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Moderator
Moderator
980 Views
Registered: ‎11-09-2015

Re: How to test AXI4-stream custom IP with master interface

Hi stu2k@msn.com,

 

No there is no documentation about the generated RTL. Only the comments inside the code.

 

Usually you interface with the AXI4 interface using registers which should already be in the code


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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