In Zynq ZC706 I am writing the data from the ethernet DMA into the Dual port Block ram ,That same block ram I am read/writing from PL also. I am not able to find when my block ram is getting full?

[p.anilraj93]

I am  new to Zynq platform.In my  Zynq ZC706 design  I am writing the data from the ethernet (GEM) peripheral DMA into the Dual port Block ramon PL side ,and to that  same block ram I am read/writing from PL also. I am not able to find when my block ram is getting full and my data is getting corrupt

can u suggest me any idea Wether to use fifo or AXI CDMA?

[demarco]

Hi @p.anilraj93,

I'm not sure what you mean by your Block RAM is getting "full." This is a memory mapped device, so it doesn't have a concept of full/empty like a FIFO. I would expect software to manage where the GEM Ethernet DMAs data and software should know how big that BRAM is as well as insure that it doesn't allow DMA to exceed the size of the BRAM.

Whether to use a FIFO or AXI CDMA depends on your application as they have very different purposes. Can you explain what problem you are trying to solve?

Generally, FIFOs are used when you have a mismatch in the data rate between a producer and a consumer. If you have a fast AXI master that can send a lot of data and a slow AXI slave that can't consume the data as quickly, you add a FIFO to hide the latency of the slave from the master.

An AXI CDMA performs memory to memory transfers. Examples of the transfers it performs are DRAM to DRAM or BRAM to DRAM. You need a processor to set up the transfer.

Regards,

Deanna