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Adventurer
Adventurer
764 Views
Registered: ‎11-27-2010

Issue in example code of cyclic mode + AXI DMA ??

Hi,

     In the xaxidma_example_sgcyclic_intr.c,

 

The cyclic mode setup of TxDMA [MM2S] does NOT follow the [AXI DMA v7.1 14 PG021 April 4, 2018]

 
"This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result
in unexpected behavior."

 

https://github.com/Xilinx/embeddedsw/blob/b2f54f649486ec1435f2f6b6e524d9c9c84f2efc/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sgcyclic_intr.c

 

Code: -

in Txsetup(), the DMA engine is started

in TxSetup() --> XAxiDma_BdRingStart() --> XAxiDma_StartBdRingHw() --> the bit of XAXIDMA_CR_RUNSTOP_MASK is set in this function

 

and in SendPacket() [a much later function in the code flow], the bit of XAXIDMA_CR_CYCLIC_MASK is set in

XAxiDma_SelectCyclicMode()

 

This goes against the Xilinx official document.

 

Thanks

 

 

 

 

mm2s_bitset.jpg
code_within.jpg
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2 Replies
Xilinx Employee
Xilinx Employee
693 Views
Registered: ‎10-04-2016

Re: Issue in example code of cyclic mode + AXI DMA ??

Hi @optivareddy,

The AXI DMA is idle when the cyclic mode bit is set in SendPacket().

 

You can verify this by reading MM2S_DMASR when you hit the SendPacket() break point. If bit 1 is set to 1, the channel is idle and it is okay to set the cyclic mode bit.

 

Regards,

 

Deanna

 

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Adventurer
Adventurer
671 Views
Registered: ‎11-27-2010

Re: Issue in example code of cyclic mode + AXI DMA ??

Hi,

    memory dump at breakpoint at SendPacket() call.

 

mrd -force 0xA0260000 20
A0260000: 640A7003 <-------[MM2S_DMACR]
A0260004: 000A0008 <-------[MM2S_DMASR]

 

000A0008 [MM2S_DMASR]

binary representation 0000 0000 0000 1010 0000 0000 0000 1000

bit 0 value : - 0

bit 1 value : - 0

//==========================//From Xilinx doc

Bit 0: 
DMA Channel Halted. Indicates the run/stop state of the DMA
channel.
0 = DMA channel running.
• 1 = DMA channel halted. 

//==========================//From Xilinx doc

Bit 1:- 
0 = Not Idle. 
• 1 = Idle. 

//==============//

bit 0 says DMA channel running and bit 1 says DMA channel Not idle.

//====================//

please let me know your re-take on this.

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