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Visitor ha8080
Visitor
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Registered: ‎05-14-2018

Large of-chip-FIFO using AXI memory controller and AXIS DataMovers

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Hello,

I am working on a design which is going to use external memory via a memory controller with AXI4 interface. The memory controller will exclusively be used to buffer an intermittent input stream for a slower readout. The buffer will fill up to several MB before being drained entirely again. For bandwidth considerations I will have to use burst transfers (>= 128 bytes). I am contemplating to convert the stream into an AXI-Stream and using a S2MM DataMover for writing and a MM2S DataMover for reading. I am rather new to this and the 7 series in general. Is this a reasonable way to instead of handcrafting a FIFO logic? Are there examples out there fro what I am trying to do?

Thanks in advance.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: Large of-chip-FIFO using AXI memory controller and AXIS DataMovers

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Hi @ha8080,

The AXI DataMover is a good candidate for what you are describing. The IP does come with an example design. See chapter 5 of the PG.

https://www.xilinx.com/support/documentation/ip_documentation/axi_datamover/v5_1/pg022_axi_datamover.pdf#page=48

You might take a look at AXI DMA as well. Internally, it uses the AXI DataMover. AXI DMA is more relevant when you have a processor available to configure it.

https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

Regards,

Deanna

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Xilinx Employee
Xilinx Employee
258 Views
Registered: ‎10-04-2016

Re: Large of-chip-FIFO using AXI memory controller and AXIS DataMovers

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Hi @ha8080,

The AXI DataMover is a good candidate for what you are describing. The IP does come with an example design. See chapter 5 of the PG.

https://www.xilinx.com/support/documentation/ip_documentation/axi_datamover/v5_1/pg022_axi_datamover.pdf#page=48

You might take a look at AXI DMA as well. Internally, it uses the AXI DataMover. AXI DMA is more relevant when you have a processor available to configure it.

https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf

Regards,

Deanna

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Visitor ha8080
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Registered: ‎05-14-2018

Re: Large of-chip-FIFO using AXI memory controller and AXIS DataMovers

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Thanks for letting me know that I am on the right track. I will now be digging into the documentation...

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