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Adventurer
Adventurer
456 Views
Registered: ‎01-26-2017

Max size of simple AXI DMA transfers

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Hi,

 

I am using a MicroBlaze design with AXI DMA driving DDR4 on the KCU105. The idea is to write a large chunk of data from the PS to the PL using the DMA in simple (no scatter-gather) mode. 

 

I have modified the simple DMA transfer example, however my transfers do not work. 

 

When I call 

 

Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) TxBufferPtr, MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);

 

it does not return XST_SUCCESS and then the rest of my code fails because this runs:

 

if (Status != XST_SUCCESS) {
xil_printf("...DMA transfer failed\n");
return XST_FAILURE;
}

 

What is the best way to transmit 327680 values (all uint32s) ? I have tried with MAX_PKT_LEN set to 327680 but it fails. Obviously there is a max size limit on a single DMA transfer, but I cannot find it in the AXI DMA logicore documention. What is the max size I can send in a single transfer? 

 

Thanks for your time

--- Estimated Development time: 2*Pi*(planned completion date) ---
1 Solution

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Visitor daba0uo
Visitor
549 Views
Registered: ‎08-01-2018

Re: Max size of simple AXI DMA transfers

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Accroding to the datasheet  "pg021_axi_dma.pdf" below,the Buffer Length Register Width parameter will be set while parameterizing the DMA IP core.

 

S2MM_LENGTH (S2MM DMA Buffer Length Register – Offset 58h)
This register provides the length in bytes of the buffer to write data from the Stream to Memory map DMA transfer.
Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.

Image.png

At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior.
Notes:
1. Width of Length field determined by Buffer Length Register Width parameter. Minimum width is 8 bits (7 to 0) and maximum width is 26 bits (25 to 0).
2 Replies
Highlighted
Visitor daba0uo
Visitor
550 Views
Registered: ‎08-01-2018

Re: Max size of simple AXI DMA transfers

Jump to solution

Accroding to the datasheet  "pg021_axi_dma.pdf" below,the Buffer Length Register Width parameter will be set while parameterizing the DMA IP core.

 

S2MM_LENGTH (S2MM DMA Buffer Length Register – Offset 58h)
This register provides the length in bytes of the buffer to write data from the Stream to Memory map DMA transfer.
Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.

Image.png

At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.
Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior.
Notes:
1. Width of Length field determined by Buffer Length Register Width parameter. Minimum width is 8 bits (7 to 0) and maximum width is 26 bits (25 to 0).
Adventurer
Adventurer
438 Views
Registered: ‎01-26-2017

Re: Max size of simple AXI DMA transfers

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@daba0uo

 

Yup, I was careless when reading the documentation and didn't see it. Thanks for the clarification - kudos and solved

 

--- Estimated Development time: 2*Pi*(planned completion date) ---
0 Kudos