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Participant bpb
Participant
357 Views
Registered: ‎09-11-2016

PS-PL I/O coherency and BROADCASTINNER

UG1085 indicates that BROADCASTINNER should be tied to 1 for cached PL masters (two-way coherency), but the wiki page [1] and AR# 69446 [2] indicate that BROADCASTINNER or outer shareable memory be used even for I/O coherent PL masters.

 

Is BROADCASTINNER or outer shareable memory actually needed for I/O coherent (non-cached) PL masters?

 

[1] http://www.wiki.xilinx.com/Zynq%20UltraScale%20MPSoC%20Cache%20Coherency

[2] https://www.xilinx.com/support/answers/69446.html

 

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Participant bpb
Participant
325 Views
Registered: ‎09-11-2016

Re: PS-PL I/O coherency and BROADCASTINNER

I suspect it is required due to the following statement in the A53 TRM section 7.2.2:

 

"If the system sends a snoop to the Cortex-A53 processor for an address that is present in the L1 or L2 cache, but the line in the cache is in a shareability domain that does not extend beyond the cluster, then the snoop is treated as missing in the cluster."

 

So, even if you issue a cacheable ARCACHE Inner Shareable ARDOMAIN transaction for a memory address that is cached in one of the A53s, BROADCASTINNER is needed to extend the Inner Shareable domain beyond the cluster of A53s.

 

It would be good to know the value of AxDOMAIN that is used for the PL HPC ports (since they're AXI4 on PL side, ACE/ACE-Lite on CCI-side).

 

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