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Participant diy_a
Participant
181 Views
Registered: ‎03-20-2017

PS to PL AXI access

Hi

 

I am using an evaluation board with ZC702 and implemented an AXI DMA in PL logic(to access DDR connected to PS). we have ported kernel 4.6.0 and used inbuilt axi dma test driver to access DMA in PL. kernel crashes when trying to access PL DMA at address 0x40400000. below is device tree configuration,

 

axi_vdma_0: axivdma@40400000{
        compatible = "xlnx,axi-dma-test-1.00.a";
        #dma-cells = <1>;
        reg = < 0x40400000 0x10000 >;
        xlnx,include-sg = <0x0>;
        dma-ranges = <0x00000000 0x00000000 0x40000000>;
        xlnx,num-fstores = <0x8>;
        xlnx,flush-fsync = <0x1>;
        xlnx,addrwidth = <0x20>;

        clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15>;
        clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk","m_axi_sg_aclk",
                      "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";

        dma-channel@40400000 {
                                compatible = "xlnx,axi-dma-mm2s-channel";
                                interrupts = < 0 61 4 >;
                                dma-channels = < 0x1 >;
                                xlnx,datawidth = <0x20>;
                                xlnx,device-id = <0x0>;
       } ;
        dma-channel@40400030 {
                                compatible = "xlnx,axi-dma-s2mm-channel";
                                dma-channels = < 0x1 >;
                                xlnx,datawidth = <0x20>;
                                xlnx,device-id = <0x0>;
        } ;
        } ;
         dmatest_0: dmatest@0 {
                        compatible ="xlnx,axi-dma-test-1.00.a";
                        dmas = <&axi_vdma_0 0
                                &axi_vdma_0 1>;
                        dma-names = "dma0", "dma1";
       } ;

any help in understanding the issue is appreciated.

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1 Reply
Moderator
Moderator
122 Views
Registered: ‎11-09-2015

Re: PS to PL AXI access

HI @diy_a,

 

Are you sure that the PL is programmed using the correct bitstream?

 

Could you try to just use xsct, program the bistream and see if you can access this address?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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