05-18-2018 10:19 AM
Hello, I just had a few quick questions.
When a "character" is stored in the axi_uartlite FIFO, is this character stored as an unsigned integer? In our case it's a 8-bit message, so is each character stored as a value from 0 to 255?
If within this character, there is a parity bit error, would this message still get transmitted/received?
In regards to address,
The uart is given a base address automatically within vivado. In my case, 0x42C0_0000 to 0x42C0_FFFF. Would each Tx and Tx message be stored in this range by some offset?
Is the offset different for each message, or is it a standard offset?
Does this relate to FIFO memory at all?
05-18-2018 10:45 AM
It's all explained here:
You can't randomly access the TX or RX messages, only write or read them sequentially, one byte at at time. From what I can tell, a parity error on reception sets a flag (or can generate an interrupt), but it's not saved in the RX Fifo.
05-21-2018 12:08 PM
05-22-2018 05:38 AM
A parity error generates a status bit, but you can't tell which character actually had the parity error. The fifo only holds 8 bits of data, and nothing about parity errors.