05-09-2019 03:24 AM
I used the standard example from the axi_ethernet directory (xaxiethernet_example_intr_sgdma) for AXI DMA in scatter gather mode. I could transmit and receive a packet.
Later, I modified the code to receive the data in promiscuous mode. I could see a single packet again. Could anyone let me know the modifications that would be required in the code to receive the packets continuously (while (1)). Whenever I tried putting the functions in a loop, I kept on receiving the packets but not without this error: AXI DMA: RX error interrupts. The error is from the RxIntrHandler function.
I ran the xaxidma_example_sg_intr.c and changed the code to run the sendpacket function in a loop and I could see the packets getting transmitted and received for the specified number of times.
After several attempts of changing the code, I am still unable to find the exact cause, could someone help me get rid of this error and receive the packets as they arrive.
06-11-2019 12:57 PM
You're going to need to dig into the code some more to figure out why you are hitting this error in order to know what to fix.
The error you are hitting occurs with the AXI DMA S2MM_DMASR register asserts the Err_Irq. Per PG021, the channel hit some non-specific error.
To get more detail into what happened, you need to look through the processed buffer descriptors to see where things went wrong. The field of interest is the S2MM_STATUS dword in the buffer descriptor. The obvious BD to start with is the one pointed to by the S2MM_CURDES registers--that's the descrptor that the AXI DMA Scatter Gather engine is processing.
For details on the AXI DMA registers and buffer descriptor formats, refer to PG021.
06-13-2019 08:48 AM
I understand that this is something similar to what I require:https://forums.xilinx.com/t5/Networking-and-Connectivity/ZEDBOARD-RECEIVE-ETHERNET-PACKETS-INDEFINITELY/td-p/839418 but the solution is relevant for internal gigabit eth controller and I am using AXI ethernet, could you suggest an alternative for this. Thanks.
06-25-2019 04:56 PM
Hi @bbhatt ,
What you are wanting to do with the example code is not a trivial change. You are going to have to dive in and really understand how the AXI DMA bare metal driver works.
The issue is in how you are post-processing and re-allocating the AXI DMA buffer descriptors. The bare metal AXI DMA driver documents its management of the BD ring here:
Perhaps running AXI DMA in cyclic mode would solve your problem. Please refer to PG021 to learn what cyclic mode is. There is a bare metal AXI DMA example that shows how to use this mode.
06-25-2019 07:48 PM
Thank you for the reply. I'm aware about the cyclic mode and wanted to confirm if I can use it to receive packets continuously ? I understand that there are fixed no. of packets that can be received using this mode, kindly let me know if I've understood it correctly.
06-26-2019 09:32 AM
Yes, you can use cyclic mode to re-use the same buffer descriptors continuously. This would be the equivalent of receiving packets continuously.
I do caution that folks tend to run into trouble in the post processing of the buffer descriptors in cyclic mode. The code has to be well tuned to make sure no packets are lost.
We actually just fixed a bug in the bare metal driver for 2019.1 because we weren't tracking completed descriptors properly.