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Visitor linux.fpga
Visitor
641 Views
Registered: ‎11-01-2018

Sending Data from PS to PL FIFO

Hello,

I want to send buffer[1024] from PS app to FIFO in PL side via AXI lite bus?

Is there any idea how this is done?

How do I know when a new data appeared on PL side?

Regards.

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Xilinx Employee
Xilinx Employee
550 Views
Registered: ‎10-04-2016

Re: Sending Data from PS to PL FIFO

Hi @linux.fpga,

Which FIFO IP are you targeting?

Generally speaking, the FIFO should have a memory mapped address location in the PL. This address will depend on which PS-PL AXI Master Port the FIFO connects to. You need to consult the Address Editor in IP Integrator to find the base address for the FIFO.

Depending on which FIFO IP you are attempting to write to, you might need to add an offset to the base address of the FIFO. 

How to determine whether there is data in your FIFO depends on the IP. Some have an empty signal that will de-assert when there is data present in the FIFO. Others might have a memory mapped register that software can query to see the condition of the FIFO.

Regards,

Deanna

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Scholar vanmierlo
Scholar
519 Views
Registered: ‎06-10-2008

Re: Sending Data from PS to PL FIFO

I suggest to use an AXI-Stream FIFO and only enable the Transmit Data channel.

When there is data available the AXI-Stream tvalid will indicate this.