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Visitor zhlimpcas
Registered: ‎10-29-2018

Smartconnect and Synchronous Clock Domain Crossing Issues


I have a issue about AXI Smartconnect IP core.

Vivado always give the CRITICAL WARNING, when create HDL wrapper, this CRITICAL WARNING as follow show:

CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] ddr3_smartconnect_0_2: The device(s) attached to /S00_AXI do not share a common clock source with this smartconnect instance.   Re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent futher clock DRC violations.

How to solve this  CRITICAL WARNING?

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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: Smartconnect and Synchronous Clock Domain Crossing Issues

Hi @zhlimpcas,

The tools have detected that the AXI master IP attached to the S00_AXI port of your SmartConnect is not in the same clock domain as the other Snn_AXI/Mnn_AXI ports on the SmartConnect. As the Critical Warning says, you need to add another input clock to your SmartConnect and tie the AXI clock associated with S00_AXI to it.

You will need to open the configuration GUI for the SmartConnect and change the number of clocks. The tools will automatically detect which AXI interface it is associated with.





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