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Adventurer
Adventurer
799 Views
Registered: ‎11-27-2010

Throughput on slave interfaces [zynq mpsoc, ultrascale+]

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Hi, 

   I am looking for Throughput figures on various slave axi interfaces 

 

two (AXI HPC0 FPD, AXI HPC1 FPD) high performance AXI I/O coherent master interfaces in full-power domain;

four (AXI HP0 FPD, AXI HP1 FPD, AXI HP2 FPD, AXI HP3 FPD) high performance slave interfaces in full-power domain;

one (AXI LPD) AXI interface in low-power domain

 

so overall 7 interfaces

 

I went through this link [http://www.wiki.xilinx.com/Zynq+UltraScale%EF%BC%8B+MPSoC+-+System+Performance+Modelling], however i dont see any FINAL report on comparison. If there is one,plz point to it.

 

===========================

Estimated Throughput= (AXI-Datawidth/8) x PL clock frequency x (Beats per transaction/Max(beats per transaction, Transaction interval))

 

so few questions on above formula

[1] Is this formula applicable to all 7 Interfaces?

[2] Assuming constant datawidth, pl clk, beats per transaction, are all 7 interfaces can have same max throughput?

[3] in this case even LPD slave is of type High Performance?

[4] when i enable new HPC<x>/HP<x> port, the Run Automation Connection shows up and it has option of selecting Master under options. [picture attached]. 

what does this Master means, is that this selected Master has preference over the bus or is it that it is the one owning the bus. plz explain.

 

 

Thanks

Master.jpg
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Xilinx Employee
Xilinx Employee
679 Views
Registered: ‎10-04-2016

Re: Throughput on slave interfaces [zynq mpsoc, ultrascale+]

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Hi @optivareddy,

The NIC-400 switch, the FPD main switch and the LPD main switch do not support out of band errors. All AXI errors would be signaled in-band with either a DECERR or SLVERR.

 

If an AXI Slave cannot service a request from an AXI Master, it will drop its AWREADY, ARREADY or WREADY signals. With PL devices, long delays between xVALID assertions and xREADY responses is how you start to discover that the system is servicing a lot of requests.

 

Bus contention isn't really an AXI concept. You can have multiple masters requesting access to the same slave via an AWVALID or ARVALID. An interconnect or switch will arbitrate which master "wins" access to the slave via a defined arbitration algorithm. No request gets dropped, but a master may not receive a response back in a timely fashion if there isn't enough bandwidth to share between all of the requesting masters.

 

Regards,

 

Deanna

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: Throughput on slave interfaces [zynq mpsoc, ultrascale+]

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Hi @optivareddy,

Yes, the formula is applicable to all 7 interfaces and yes, all 7 interfaces could have the same maximum throughput for the situation you describe. The S_AXI_LPD port has the same is capable of the same performance as the S_AXI_HPn_FPD and S_AXI_HPCn_FPD ports.

 

In your screenshot, the Connection Automation wizard is providing guidance for which AXI Master should drive the S_AXI_HPC1_FPD port. It surveyed the available AXI Masters in the PL and provided the m_dest_axi port on the axi_ad9361 IP as a candidate. It looks like there might be other masters available that could connect to this port. 

 

An AXI Master can initiate a read or write transaction. An AXI Slave responds to the read or write transaction. A typical AXI Master is a processor or DMA. A typical AXI Slave is a memory or peripheral. Multiple masters can send read/write commands to a single slave. An AXI Interconnect or SmartConnect in the PL arbitrates when multiple masters request access to the same slave at the same time.

 

For further details on how AXI works, please refer to UG1037, the Vivado AXI Reference Guide.

https://www.xilinx.com/support/documentation/ip_documentation/axi_ref_guide/latest/ug1037-vivado-axi-reference-guide.pdf

 

Regards,

 

Deanna

 

 

 

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Adventurer
Adventurer
691 Views
Registered: ‎11-27-2010

Re: Throughput on slave interfaces [zynq mpsoc, ultrascale+]

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Hi Deanna,

                 Thanks for response.

 

does AXI HP interconnect switch throw errors/set flags when it is unable to keep with read/write transaction from multiple AXI Masters ?

In other words, under bus contention condition, does AXI HP interconnect signal the status of contention in any of its status registers or ports ?

 

how about internal switches like FPD main switch, LPD main switch [figure 15-1 Top-level interconnect architecture ultrasacle trm UG 1085 v1.7] and other internal data switches like 

1. switch between display port and HP0_FPD

2. switch between HP1 and HP2

3. switch between FP DMA and HP3_FPD 

how to identify bus contention in those switches?

 

Thanks

 

 

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Xilinx Employee
Xilinx Employee
680 Views
Registered: ‎10-04-2016

Re: Throughput on slave interfaces [zynq mpsoc, ultrascale+]

Jump to solution

Hi @optivareddy,

The NIC-400 switch, the FPD main switch and the LPD main switch do not support out of band errors. All AXI errors would be signaled in-band with either a DECERR or SLVERR.

 

If an AXI Slave cannot service a request from an AXI Master, it will drop its AWREADY, ARREADY or WREADY signals. With PL devices, long delays between xVALID assertions and xREADY responses is how you start to discover that the system is servicing a lot of requests.

 

Bus contention isn't really an AXI concept. You can have multiple masters requesting access to the same slave via an AWVALID or ARVALID. An interconnect or switch will arbitrate which master "wins" access to the slave via a defined arbitration algorithm. No request gets dropped, but a master may not receive a response back in a timely fashion if there isn't enough bandwidth to share between all of the requesting masters.

 

Regards,

 

Deanna

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