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Visitor sjh@notts
Visitor
5,207 Views
Registered: ‎04-22-2016

Vivado 2015.4 AXI narrow burst support

I have a design using the PCIe memory mapped IP block and CDMA on the ZC706 board using Vivad0 2015.4, which works.

However I now want to add some custom processing between the PCIe IP and the AXI interconnect IP that provides connection to the ARM AXI HP0 & CDMA IP.

This will have full S-AXI & M-AXI ports to connect to the PCIe IP & full S-AXI & M-AXI ports connecting onwards to the CDMA & ARM etc.

 

I have created the skeleton VHDL for this custom logic using the 'create & package IP' tool from vivado and have integrated into the block diagram.

However when I verify it generates the critical warnings

Vivado Commands

  validate_bd_design -force
    [BD 41-237] Bus Interface property SUPPORTS_NARROW_BURST does not match between /nexor_demo_0/S01_AXI_PCI(0) and /axi_pcie_0/M_AXI(1)
    [BD 41-237] Bus Interface property SUPPORTS_NARROW_BURST does not match between /nexor_demo_0/S00_AXI(0) and /axi_interconnect_0/m01_couplers/m01_data_fifo/M_AXI(1)

 

Based on AR# 57882 I tried to create & define the control SUPPORTS_NARROW_BURSTS and set to 0 but this does not fix the problem, though I note this was for earlier versions of Vivado.

 

I can find no other reference to anything that might control this capability (I do not want to support narrow bursts) except a line in the *.xml file for the custom IP, but I ma not sure if that is the place to modify this feature.

 

Thanks for any guidance 

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Contributor
Contributor
401 Views
Registered: ‎09-19-2017

Re: Vivado 2015.4 AXI narrow burst support

I have encountered the same problem in SDS0C2017.1. Have you solved this problem?

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