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Participant tmaintz
Participant
92 Views
Registered: ‎12-26-2016

Zynq AXI BRAM to scattered DDR Addresses by custom AXI Master IP

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Hi there,

I want to implement a BRAM to DDR datamover. Each address of the BRAM represents channel data for later FFT conversions (at maximum 256 different channels). The BRAM itself is a buffer for my whole design. Frequencies of the channel data are around 100kHz, my FPGA runs roughly at 145MHz.

The Xilinx FFT Core expects an AXI-Stream format, so it would be efficient to sort the BRAM data into specific DDR addresses when I transfer them. Right now I want to use the address pattern like this:

BitpositionMode
15:8Channel ID
7:0Cycle Iteration

With a later used DMA ScatterGather IP Core it's easy to read a chunk of data and do the FFT calculation because data is aligned within the DDR memory.

I've written a custom AXI4-L Master IP and connected it to the GP0 (and later the HP1) port of the Zynq. To get started I took the AXI4-L Master template from Vivado and changed the core to my needs, (there are only single transactions possible). Sadly the design needs way too much FPGA clock cycles to finish, at the GP0 it needs around 30-48 cycles the HP1 performs at 20-30 cycles.

AXIM_Transactions.png

Now I want to change my design for a higher AXI throughput. There are several options in my head to achieve my goals:

  • Use a AXI DMA SG for scattering the data into specific source but how can I change the address increment?
  • Write an AXI Full block to enable burst mode. I found nothing about the WRAP mode and its increment value possibilities
  • Use the CDMA (by designing the custom core I wanted to skip that...)

Attached is the current source of the AXI Datamover. The BusManager_Node entity is the BRAM where you get the data by the data_* signals. All the bus_* are connected to my data bus. Thanks for any advice on my design!

Regards,
Thomas

 

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Participant tmaintz
Participant
27 Views
Registered: ‎12-26-2016

Re: Zynq AXI BRAM to scattered DDR Addresses by custom AXI Master IP

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Buffer some data and write them in bursts is the better option for throughput. Neither updating the FSBL nor the address range had some impact on my results.

Greetings

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1 Reply
Participant tmaintz
Participant
28 Views
Registered: ‎12-26-2016

Re: Zynq AXI BRAM to scattered DDR Addresses by custom AXI Master IP

Jump to solution

Buffer some data and write them in bursts is the better option for throughput. Neither updating the FSBL nor the address range had some impact on my results.

Greetings

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