01-18-2019 10:48 AM
I have very basic question:
- Zynq Ultrascale Soc has DMA Controller(s) (in PS).
- in PL, AXI DMA Controller IP is used for dma xfers.
Are both dma controllers used in the design or only one is used at any time to implement the dma xfers?
01-21-2019 11:19 AM
Depending on your design you could use both or one or the other. It really depends on what you want to do. Some examples could be including multiple AXI DMA IPs in a single design to transmit to two seperate output data streams, or using an AXI DMA IP in conjunction with the PS DMA (ZDMA) to access data from both DDR and BRAM at the same time. With multiple DMA at the same time there can be issues with arbitration, leading to some difficult design decisions in order to access or send out data efficiently.
This link has a post by @jg_bds about DMA which might be worth reading:
01-21-2019 12:16 PM
Thank you very much for your response.
Now I have a question about linux drivers for dma:
If I want to use ps dma controller, then the linux driver to be used is xilinx's dma engine client driver.
But if I use AXI DMA IP Softcore, I can use UIO driver.
Can you please let me know if this is correct or any other thoughts.
01-21-2019 02:37 PM - edited 01-21-2019 02:38 PM
Xilinx provides Linux drivers for both the hard DMA IPs and the soft DMA IPs.
The full list of drivers are here:
These are kernel drivers. This Wiki article explains how you could use them to perform transfers from user space. Even though the article is specific to AXI DMA, you could do something similar with the PS DMAs.